Subzero. Enables (most) crosstests for ARM32.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 15 matching lines @@
 namespace Ice {
 
 namespace {
 
 const struct TypeARM32Attributes_ {
   const char *WidthString;    // b, h, <blank>, or d
   const char *VecWidthString; // i8, i16, i32, f32, f64
   int8_t SExtAddrOffsetBits;
   int8_t ZExtAddrOffsetBits;
 } TypeARM32Attributes[] = {
-#define X(tag, elementty, int_width, vec_width, sbits, ubits)                  \
+#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr)          \
   { int_width, vec_width, sbits, ubits }                                       \
   ,
     ICETYPEARM32_TABLE
 #undef X
 };
 
 const struct InstARM32ShiftAttributes_ {
   const char *EmitString;
 } InstARM32ShiftAttributes[] = {
 #define X(tag, emit)                                                           \
@@ skipping 157 matching lines @@
   Vars[1] = Index;
 }
 
 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) {
   int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits
                          : TypeARM32Attributes[Ty].ZExtAddrOffsetBits;
   if (Bits == 0)
     return Offset == 0;
   // Note that encodings for offsets are sign-magnitude for ARM, so we check
   // with IsAbsoluteUint().
-  if (isScalarFloatingType(Ty))
-    return Utils::IsAligned(Offset, 4) && Utils::IsAbsoluteUint(Bits, Offset);
+  /*if (isScalarFloatingType(Ty))

[Jim Stichnoth, 2015/09/24 05:57:13]

Explain or delete comment?

[John, 2015/09/24 21:28:39]

Done.

+    return Utils::IsAligned(Offset, 4) && Utils::IsAbsoluteUint(Bits, Offset);*/
   return Utils::IsAbsoluteUint(Bits, Offset);
 }
 
 OperandARM32FlexImm::OperandARM32FlexImm(Cfg * /* Func */, Type Ty,
                                          uint32_t Imm, uint32_t RotateAmt)
     : OperandARM32Flex(kFlexImm, Ty), Imm(Imm), RotateAmt(RotateAmt) {
   NumVars = 0;
   Vars = nullptr;
 }
 
@@ skipping 159 matching lines @@
 InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vcmp, 2, nullptr, Predicate) {
   addSource(Src0);
   addSource(Src1);
 }
 
 InstARM32Vmrs::InstARM32Vmrs(Cfg *Func, CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {}
 
+InstARM32Vabs::InstARM32Vabs(Cfg *Func, Variable *Dest, Variable *Src,
+                             CondARM32::Cond Predicate)
+    : InstARM32Pred(Func, InstARM32::Vabs, 1, Dest, Predicate) {
+  addSource(Src);
+}
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Clz::Opcode = "clz";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 template <> const char *InstARM32Rbit::Opcode = "rbit";
 template <> const char *InstARM32Rev::Opcode = "rev";
 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h
 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h
 // FP
 template <> const char *InstARM32Vsqrt::Opcode = "vsqrt";
 // Mov-like ops
 template <> const char *InstARM32Ldr::Opcode = "ldr";
-template <> const char *InstARM32Mov::Opcode = "mov";
-// FP
-template <> const char *InstARM32Vldr::Opcode = "vldr";
 // Three-addr ops
 template <> const char *InstARM32Adc::Opcode = "adc";
 template <> const char *InstARM32Add::Opcode = "add";
 template <> const char *InstARM32And::Opcode = "and";
 template <> const char *InstARM32Asr::Opcode = "asr";
 template <> const char *InstARM32Bic::Opcode = "bic";
 template <> const char *InstARM32Eor::Opcode = "eor";
 template <> const char *InstARM32Lsl::Opcode = "lsl";
 template <> const char *InstARM32Lsr::Opcode = "lsr";
 template <> const char *InstARM32Mul::Opcode = "mul";
@@ skipping 16 matching lines @@
 template <> const char *InstARM32Tst::Opcode = "tst";
 
 void InstARM32::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "[ARM32] ";
   Inst::dump(Func);
 }
 
-template <> void InstARM32Mov::emit(const Cfg *Func) const {
+void InstARM32Mov::emitMultiDestSingleSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
-  assert(getSrcSize() == 1);
-  Variable *Dest = getDest();
-  if (Dest->hasReg()) {
-    IceString ActualOpcode = Opcode;
-    Operand *Src0 = getSrc(0);
-    if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) {
-      if (!Src0V->hasReg()) {
-        // Always use the whole stack slot. A 32-bit load has a larger range of
-        // offsets than 16-bit, etc.
-        ActualOpcode = IceString("ldr");
-      }
-    } else {
-      if (llvm::isa<OperandARM32Mem>(Src0))
-        ActualOpcode = IceString("ldr") + getWidthString(Dest->getType());
-    }
-    Str << "\t" << ActualOpcode << getPredicate() << "\t";
-    getDest()->emit(Func);
-    Str << ", ";
-    getSrc(0)->emit(Func);
-  } else {
-    Variable *Src0 = llvm::cast<Variable>(getSrc(0));
-    assert(Src0->hasReg());
-    Str << "\t"
-        << "str" << getPredicate() << "\t";
-    Src0->emit(Func);
-    Str << ", ";
-    Dest->emit(Func);
-  }
+  auto *Dest = llvm::cast<Variable64On32>(getDest());
+  Operand *Src = getSrc(0);
+
+  assert(Dest->getType() == IceType_i64);
+  assert(Dest->getHi()->hasReg());
+  assert(Dest->getLo()->hasReg());
+  assert(!llvm::isa<OperandARM32Mem>(Src));
+
+  Str << "\t"
+      << "vmov" << getPredicate() << "\t";
+  Dest->getLo()->emit(Func);
+  Str << ", ";
+  Dest->getHi()->emit(Func);
+  Str << ", ";
+  Src->emit(Func);
 }
 
-template <> void InstARM32Mov::emitIAS(const Cfg *Func) const {
-  assert(getSrcSize() == 1);
-  (void)Func;
-  llvm_unreachable("Not yet implemented");
-}
-
-template <> void InstARM32Vldr::emit(const Cfg *Func) const {
+void InstARM32Mov::emitSingleDestMultiSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
-  assert(getSrcSize() == 1);
-  assert(getDest()->hasReg());
-  Str << "\t" << Opcode << getPredicate() << "\t";
-  getDest()->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
-}
+  Variable *Dest = getDest();
+  auto *Src = llvm::cast<Variable64On32>(getSrc(0));
 
-template <> void InstARM32Vldr::emitIAS(const Cfg *Func) const {
-  assert(getSrcSize() == 1);
-  (void)Func;
-  llvm_unreachable("Not yet implemented");
-}
-
-void InstARM32Vmov::emitMultiDestSingleSource(const Cfg *Func) const {
-  if (!BuildDefs::dump())
-    return;
-  Ostream &Str = Func->getContext()->getStrEmit();
-  Variable *Dest0 = getDest();
-  Operand *Src0 = getSrc(0);
-
-  assert(Dest0->hasReg());
-  assert(Dest1->hasReg());
-  assert(!llvm::isa<OperandARM32Mem>(Src0));
+  assert(Src->getType() == IceType_i64);
+  assert(Src->getHi()->hasReg());
+  assert(Src->getLo()->hasReg());
+  assert(Dest->hasReg());
 
   Str << "\t"
       << "vmov" << getPredicate() << "\t";
-  Dest0->emit(Func);
+  Dest->emit(Func);
   Str << ", ";
-  Dest1->emit(Func);
+  Src->getLo()->emit(Func);
   Str << ", ";
-  Src0->emit(Func);
-}
-
-void InstARM32Vmov::emitSingleDestMultiSource(const Cfg *Func) const {
-  if (!BuildDefs::dump())
-    return;
-  Ostream &Str = Func->getContext()->getStrEmit();
-  Variable *Dest0 = getDest();
-  Operand *Src0 = getSrc(0);
-  Operand *Src1 = getSrc(1);
-
-  assert(Dest0->hasReg());
-  assert(!llvm::isa<OperandARM32Mem>(Src0));
-  assert(!llvm::isa<OperandARM32Mem>(Src1));
-
-  Str << "\t"
-      << "vmov" << getPredicate() << "\t";
-  Dest0->emit(Func);
-  Str << ", ";
-  Src0->emit(Func);
-  Str << ", ";
-  Src1->emit(Func);
+  Src->getHi()->emit(Func);
 }
 
 namespace {
+
 bool isVariableWithoutRegister(const Operand *Op) {
   if (const auto *OpV = llvm::dyn_cast<const Variable>(Op)) {
     return !OpV->hasReg();
   }
   return false;
 }
-
 bool isMemoryAccess(Operand *Op) {
   return isVariableWithoutRegister(Op) || llvm::isa<OperandARM32Mem>(Op);
 }
 
 bool isMoveBetweenCoreAndVFPRegisters(Variable *Dest, Operand *Src) {
   const Type DestTy = Dest->getType();
   const Type SrcTy = Src->getType();
-  assert(!(isScalarIntegerType(DestTy) && isScalarIntegerType(SrcTy)) &&
-         "At most one of vmov's operands can be a core register.");
-  return isScalarIntegerType(DestTy) || isScalarIntegerType(SrcTy);
+  return !isVectorType(DestTy) && !isVectorType(SrcTy) &&
+         (isScalarIntegerType(DestTy) == isScalarFloatingType(SrcTy));
 }
+
 } // end of anonymous namespace
 
-void InstARM32Vmov::emitSingleDestSingleSource(const Cfg *Func) const {
+void InstARM32Mov::emitSingleDestSingleSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
+
   if (Dest->hasReg()) {
+    Type DestTy = Dest->getType();
     Operand *Src0 = getSrc(0);
-    const char *ActualOpcode = isMemoryAccess(Src0) ? "vldr" : "vmov";
+    const bool DestIsVector = isVectorType(DestTy);
+    const bool DestIsScalarFP = isScalarFloatingType(Dest->getType());
+    const bool CoreVFPMove = isMoveBetweenCoreAndVFPRegisters(Dest, Src0);
+    const char *LoadOpcode =
+        DestIsVector ? "vld1" : (DestIsScalarFP ? "vldr" : "ldr");
+    const char *RegMovOpcode =
+        (DestIsVector || DestIsScalarFP || CoreVFPMove) ? "vmov" : "mov";
+    const char *ActualOpcode = isMemoryAccess(Src0) ? LoadOpcode : RegMovOpcode;
     // when vmov{c}'ing, we need to emit a width string. Otherwise, the
     // assembler might be tempted to assume we want a vector vmov{c}, and that
     // is disallowed because ARM.
+    const char *NoWidthString = "";
     const char *WidthString =
-        (isMemoryAccess(Src0) || isMoveBetweenCoreAndVFPRegisters(Dest, Src0))
-            ? ""
-            : getVecWidthString(Src0->getType());
+        isMemoryAccess(Src0)
+            ? (DestIsVector ? ".64" : NoWidthString)
+            : (!CoreVFPMove ? getVecWidthString(DestTy) : NoWidthString);
+
     Str << "\t" << ActualOpcode << getPredicate() << WidthString << "\t";
     Dest->emit(Func);
     Str << ", ";
     Src0->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
-    Str << "\t"
-           "vstr" << getPredicate() << "\t";
+    const char *ActualOpcode =
+        isVectorType(Src0->getType())
+            ? "vst1"
+            : (isScalarFloatingType(Src0->getType()) ? "vstr" : "str");
+    const char *NoWidthString = "";
+    const char *WidthString =
+        isVectorType(Src0->getType()) ? ".64" : NoWidthString;
+    Str << "\t" << ActualOpcode << getPredicate() << WidthString << "\t";
     Src0->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   }
 }
 
-void InstARM32Vmov::emit(const Cfg *Func) const {
+void InstARM32Mov::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  assert(isMultiDest() + isMultiSource() <= 1 && "Invalid vmov type.");
+  assert(!(isMultiDest() && isMultiSource()) && "Invalid vmov type.");
   if (isMultiDest()) {
     emitMultiDestSingleSource(Func);
     return;
   }
 
   if (isMultiSource()) {
     emitSingleDestMultiSource(Func);
     return;
   }
 
   emitSingleDestSingleSource(Func);
 }
 
-void InstARM32Vmov::emitIAS(const Cfg *Func) const {
+void InstARM32Mov::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
-void InstARM32Vmov::dump(const Cfg *Func) const {
+void InstARM32Mov::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
+  assert(getSrcSize() == 1);
   Ostream &Str = Func->getContext()->getStrDump();
-  dumpOpcodePred(Str, "vmov", getDest()->getType());
+  Variable *Dest = getDest();
+  if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
+    Dest64->getLo()->dump(Func);
+    Str << ", ";
+    Dest64->getHi()->dump(Func);
+  } else {
+    Dest->dump(Func);
+  }
+
+  dumpOpcodePred(Str, " = mov", getDest()->getType());
   Str << " ";
-  dumpDest(Func);
-  Str << ", ";
-  dumpSources(Func);
+
+  Operand *Src = getSrc(0);
+  if (auto *Src64 = llvm::dyn_cast<Variable64On32>(Src)) {
+    Src64->getLo()->dump(Func);
+    Str << ", ";
+    Src64->getHi()->dump(Func);
+  } else {
+    Src->dump(Func);
+  }
 }
 
 void InstARM32Br::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
       << "b" << getPredicate() << "\t";
   if (Label) {
     Str << Label->getName(Func);
@@ skipping 99 matching lines @@
   Ostream &Str = Func->getContext()->getStrDump();
   Str << getName(Func) << ":";
 }
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
-  Type Ty = getSrc(0)->getType();
-  Str << "\t" << Opcode << getWidthString(Ty) << getPredicate() << "\t";
+  Variable *Dest = getDest();
+  Type DestTy = Dest->getType();
+  const bool DestIsVector = isVectorType(DestTy);
+  const bool DestIsScalarFloat = isScalarFloatingType(DestTy);
+  const char *ActualOpcode =
+      DestIsVector ? "vld1" : (DestIsScalarFloat ? "vldr" : "ldr");
+  const char *VectorMarker = DestIsVector ? ".64" : "";
+  const char *WidthString = DestIsVector ? "" : getWidthString(DestTy);
+  Str << "\t" << ActualOpcode << WidthString << getPredicate() << VectorMarker
+      << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 template <> void InstARM32Ldr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
@@ skipping 29 matching lines @@
     Str << "#:upper16:";
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     Src1->emit(Func);
   }
 }
 
 void InstARM32Pop::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  assert(Dests.size() > 0);
+  SizeT IntegerCount = 0;
+  for (const Operand *Op : Dests) {
+    if (isScalarIntegerType(Op->getType())) {
+      ++IntegerCount;
+    }
+  }
   Ostream &Str = Func->getContext()->getStrEmit();
+  if (IntegerCount == 0) {
+    Str << "\t@ empty pop";
+    return;
+  }
   Str << "\t"
       << "pop"
       << "\t{";
-  for (SizeT I = 0; I < Dests.size(); ++I) {
-    if (I > 0)
-      Str << ", ";
-    Dests[I]->emit(Func);
+  bool PrintComma = false;
+  for (const Operand *Op : Dests) {
+    if (isScalarIntegerType(Op->getType())) {
+      if (PrintComma)
+        Str << ", ";
+      Op->emit(Func);
+      PrintComma = true;
+    }
   }
   Str << "}";
 }
 
 void InstARM32Pop::emitIAS(const Cfg *Func) const {
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
 void InstARM32Pop::dump(const Cfg *Func) const {
@@ skipping 38 matching lines @@
   getDest()->dump(Func);
   Str << " = sub.i32 ";
   getSrc(0)->dump(Func);
   Str << ", " << Amount << " ; ";
   getSrc(1)->dump(Func);
 }
 
 void InstARM32Push::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  assert(getSrcSize() > 0);
+  SizeT IntegerCount = 0;
+  for (SizeT i = 0; i < getSrcSize(); ++i) {
+    if (isScalarIntegerType(getSrc(i)->getType())) {
+      ++IntegerCount;
+    }
+  }
   Ostream &Str = Func->getContext()->getStrEmit();
+  if (IntegerCount == 0) {
+    Str << "\t"
+        << "@empty push";
+    return;
+  }
   Str << "\t"
       << "push"
       << "\t{";
-  emitSources(Func);
+  bool PrintComma = false;
+  for (SizeT i = 0; i < getSrcSize(); ++i) {
+    Operand *Op = getSrc(i);
+    if (isScalarIntegerType(Op->getType())) {
+      if (PrintComma)
+        Str << ", ";
+      Op->emit(Func);
+      PrintComma = true;
+    }
+  }
   Str << "}";
 }
 
 void InstARM32Push::emitIAS(const Cfg *Func) const {
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
 void InstARM32Push::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 31 matching lines @@
   Str << "ret." << Ty << " ";
   dumpSources(Func);
 }
 
 void InstARM32Str::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Type Ty = getSrc(0)->getType();
-  const char *Opcode = isScalarFloatingType(Ty) ? "vstr" : "str";
-  Str << "\t" << Opcode << getWidthString(Ty) << getPredicate() << "\t";
+  const bool IsVectorStore = isVectorType(Ty);
+  const char *Opcode =
+      IsVectorStore ? "vst1" : (isScalarFloatingType(Ty) ? "vstr" : "str");
+  const char *VecEltWidthString = IsVectorStore ? ".64" : "";
+  Str << "\t" << Opcode << getWidthString(Ty) << getPredicate()
+      << VecEltWidthString << "\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
 }
 
 void InstARM32Str::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
@@ skipping 174 matching lines @@
 }
 
 void InstARM32Vmrs::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "APSR{n,z,v,c} = vmrs" << getPredicate() << "\t"
                                                      "FPSCR{n,z,c,v}";
 }
 
+void InstARM32Vabs::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 1);
+  Str << "\t"
+         "vabs" << getPredicate() << getVecWidthString(getSrc(0)->getType())
+      << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+}
+
+void InstARM32Vabs::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Vabs::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  dumpDest(Func);
+  Str << " = vabs" << getPredicate() << getVecWidthString(getSrc(0)->getType());
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
-    Str << "], ";
+    Str << "]";
     break;
   default:
-    Str << ", ";
     break;
   }
   if (isRegReg()) {
+    Str << ", ";
     if (isNegAddrMode()) {
       Str << "-";
     }
     getIndex()->emit(Func);
     if (getShiftOp() != kNoShift) {
       Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #"
           << getShiftAmt();
     }
   } else {
-    getOffset()->emit(Func);
+    ConstantInteger32 *Offset = getOffset();
+    if (Offset && Offset->getValue() != 0) {
+      Str << ", ";
+      Offset->emit(Func);
+    }
   }
   switch (getAddrMode()) {
   case Offset:
   case NegOffset:
     Str << "]";
     break;
   case PreIndex:
   case NegPreIndex:
     Str << "]!";
     break;
@@ skipping 70 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice