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Side by Side Diff: src/compiler/ppc/instruction-codes-ppc.h

Issue 1356913002: [turbofan] Add support for reinterpreting integers as floating point and vice versa. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rename ReinterpretAs to BitcastTo Created 5 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 68 matching lines...) Expand 10 before | Expand all | Expand 10 after
79 V(PPC_Uint32ToDouble) \ 79 V(PPC_Uint32ToDouble) \
80 V(PPC_Float32ToDouble) \ 80 V(PPC_Float32ToDouble) \
81 V(PPC_DoubleToInt32) \ 81 V(PPC_DoubleToInt32) \
82 V(PPC_DoubleToUint32) \ 82 V(PPC_DoubleToUint32) \
83 V(PPC_DoubleToFloat32) \ 83 V(PPC_DoubleToFloat32) \
84 V(PPC_DoubleExtractLowWord32) \ 84 V(PPC_DoubleExtractLowWord32) \
85 V(PPC_DoubleExtractHighWord32) \ 85 V(PPC_DoubleExtractHighWord32) \
86 V(PPC_DoubleInsertLowWord32) \ 86 V(PPC_DoubleInsertLowWord32) \
87 V(PPC_DoubleInsertHighWord32) \ 87 V(PPC_DoubleInsertHighWord32) \
88 V(PPC_DoubleConstruct) \ 88 V(PPC_DoubleConstruct) \
89 V(PPC_BitcastDL) \
90 V(PPC_BitcastLD) \
89 V(PPC_LoadWordS8) \ 91 V(PPC_LoadWordS8) \
90 V(PPC_LoadWordU8) \ 92 V(PPC_LoadWordU8) \
91 V(PPC_LoadWordS16) \ 93 V(PPC_LoadWordS16) \
92 V(PPC_LoadWordU16) \ 94 V(PPC_LoadWordU16) \
93 V(PPC_LoadWordS32) \ 95 V(PPC_LoadWordS32) \
94 V(PPC_LoadWord64) \ 96 V(PPC_LoadWord64) \
95 V(PPC_LoadFloat32) \ 97 V(PPC_LoadFloat32) \
96 V(PPC_LoadDouble) \ 98 V(PPC_LoadDouble) \
97 V(PPC_StoreWord8) \ 99 V(PPC_StoreWord8) \
98 V(PPC_StoreWord16) \ 100 V(PPC_StoreWord16) \
(...skipping 19 matching lines...) Expand all
118 // MRR = [register + register] 120 // MRR = [register + register]
119 #define TARGET_ADDRESSING_MODE_LIST(V) \ 121 #define TARGET_ADDRESSING_MODE_LIST(V) \
120 V(MRI) /* [%r0 + K] */ \ 122 V(MRI) /* [%r0 + K] */ \
121 V(MRR) /* [%r0 + %r1] */ 123 V(MRR) /* [%r0 + %r1] */
122 124
123 } // namespace compiler 125 } // namespace compiler
124 } // namespace internal 126 } // namespace internal
125 } // namespace v8 127 } // namespace v8
126 128
127 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 129 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
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