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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1356913002: [turbofan] Add support for reinterpreting integers as floating point and vice versa. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rename ReinterpretAs to BitcastTo Created 5 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 70 matching lines...) Expand 10 before | Expand all | Expand 10 after
81 V(Mips64Lhu) \ 81 V(Mips64Lhu) \
82 V(Mips64Sh) \ 82 V(Mips64Sh) \
83 V(Mips64Ld) \ 83 V(Mips64Ld) \
84 V(Mips64Lw) \ 84 V(Mips64Lw) \
85 V(Mips64Sw) \ 85 V(Mips64Sw) \
86 V(Mips64Sd) \ 86 V(Mips64Sd) \
87 V(Mips64Lwc1) \ 87 V(Mips64Lwc1) \
88 V(Mips64Swc1) \ 88 V(Mips64Swc1) \
89 V(Mips64Ldc1) \ 89 V(Mips64Ldc1) \
90 V(Mips64Sdc1) \ 90 V(Mips64Sdc1) \
91 V(Mips64BitcastDL) \
92 V(Mips64BitcastLD) \
91 V(Mips64Float64ExtractLowWord32) \ 93 V(Mips64Float64ExtractLowWord32) \
92 V(Mips64Float64ExtractHighWord32) \ 94 V(Mips64Float64ExtractHighWord32) \
93 V(Mips64Float64InsertLowWord32) \ 95 V(Mips64Float64InsertLowWord32) \
94 V(Mips64Float64InsertHighWord32) \ 96 V(Mips64Float64InsertHighWord32) \
95 V(Mips64Push) \ 97 V(Mips64Push) \
96 V(Mips64StoreToStackSlot) \ 98 V(Mips64StoreToStackSlot) \
97 V(Mips64StackClaim) \ 99 V(Mips64StackClaim) \
98 V(Mips64StoreWriteBarrier) 100 V(Mips64StoreWriteBarrier)
99 101
100 102
(...skipping 14 matching lines...) Expand all
115 #define TARGET_ADDRESSING_MODE_LIST(V) \ 117 #define TARGET_ADDRESSING_MODE_LIST(V) \
116 V(MRI) /* [%r0 + K] */ \ 118 V(MRI) /* [%r0 + K] */ \
117 V(MRR) /* [%r0 + %r1] */ 119 V(MRR) /* [%r0 + %r1] */
118 120
119 121
120 } // namespace compiler 122 } // namespace compiler
121 } // namespace internal 123 } // namespace internal
122 } // namespace v8 124 } // namespace v8
123 125
124 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 126 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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