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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 1356913002: [turbofan] Add support for reinterpreting integers as floating point and vice versa. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rename ReinterpretAs to BitcastTo Created 5 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 97 matching lines...) Expand 10 before | Expand all | Expand 10 after
108 V(Arm64Float64ToFloat32) \ 108 V(Arm64Float64ToFloat32) \
109 V(Arm64Float64ToInt32) \ 109 V(Arm64Float64ToInt32) \
110 V(Arm64Float64ToUint32) \ 110 V(Arm64Float64ToUint32) \
111 V(Arm64Int32ToFloat64) \ 111 V(Arm64Int32ToFloat64) \
112 V(Arm64Uint32ToFloat64) \ 112 V(Arm64Uint32ToFloat64) \
113 V(Arm64Float64ExtractLowWord32) \ 113 V(Arm64Float64ExtractLowWord32) \
114 V(Arm64Float64ExtractHighWord32) \ 114 V(Arm64Float64ExtractHighWord32) \
115 V(Arm64Float64InsertLowWord32) \ 115 V(Arm64Float64InsertLowWord32) \
116 V(Arm64Float64InsertHighWord32) \ 116 V(Arm64Float64InsertHighWord32) \
117 V(Arm64Float64MoveU64) \ 117 V(Arm64Float64MoveU64) \
118 V(Arm64U64MoveFloat64) \
118 V(Arm64LdrS) \ 119 V(Arm64LdrS) \
119 V(Arm64StrS) \ 120 V(Arm64StrS) \
120 V(Arm64LdrD) \ 121 V(Arm64LdrD) \
121 V(Arm64StrD) \ 122 V(Arm64StrD) \
122 V(Arm64Ldrb) \ 123 V(Arm64Ldrb) \
123 V(Arm64Ldrsb) \ 124 V(Arm64Ldrsb) \
124 V(Arm64Strb) \ 125 V(Arm64Strb) \
125 V(Arm64Ldrh) \ 126 V(Arm64Ldrh) \
126 V(Arm64Ldrsh) \ 127 V(Arm64Ldrsh) \
127 V(Arm64Strh) \ 128 V(Arm64Strh) \
(...skipping 27 matching lines...) Expand all
155 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ 156 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \
156 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \ 157 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \
157 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \ 158 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \
158 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ 159 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */
159 160
160 } // namespace internal 161 } // namespace internal
161 } // namespace compiler 162 } // namespace compiler
162 } // namespace v8 163 } // namespace v8
163 164
164 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 165 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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