Subzero. ARM32 Fcmp lowering.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 364 matching lines @@
   addSource(Src1);
 }
 
 InstARM32Vcvt::InstARM32Vcvt(Cfg *Func, Variable *Dest, Variable *Src,
                              VcvtVariant Variant, CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vcvt, 1, Dest, Predicate),
       Variant(Variant) {
   addSource(Src);
 }
 
+InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
+                             CondARM32::Cond Predicate)
+    : InstARM32Pred(Func, InstARM32::Vcmp, 2, nullptr, Predicate) {
+  addSource(Src0);
+  addSource(Src1);
+}
+
+InstARM32Vmrs::InstARM32Vmrs(Cfg *Func, CondARM32::Cond Predicate)
+    : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {}
+
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Clz::Opcode = "clz";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 template <> const char *InstARM32Rbit::Opcode = "rbit";
 template <> const char *InstARM32Rev::Opcode = "rev";
@@ skipping 105 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest0 = getDest();
   Operand *Src0 = getSrc(0);
 
   assert(Dest0->hasReg());
   assert(Dest1->hasReg());
   assert(!llvm::isa<OperandARM32Mem>(Src0));
 
   Str << "\t"
-      << "vmov"
-      << "\t";
+      << "vmov" << getPredicate() << "\t";
   Dest0->emit(Func);
   Str << ", ";
   Dest1->emit(Func);
   Str << ", ";
   Src0->emit(Func);
 }
 
 void InstARM32Vmov::emitSingleDestMultiSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest0 = getDest();
   Operand *Src0 = getSrc(0);
   Operand *Src1 = getSrc(1);
 
   assert(Dest0->hasReg());
   assert(!llvm::isa<OperandARM32Mem>(Src0));
   assert(!llvm::isa<OperandARM32Mem>(Src1));
 
   Str << "\t"
-      << "vmov"
-      << "\t";
+      << "vmov" << getPredicate() << "\t";
   Dest0->emit(Func);
   Str << ", ";
   Src0->emit(Func);
   Str << ", ";
   Src1->emit(Func);
 }
 
 namespace {
 bool isVariableWithoutRegister(const Operand *Op) {
   if (const auto *OpV = llvm::dyn_cast<const Variable>(Op)) {
     return !OpV->hasReg();
   }
   return false;
 }
 
 bool isMemoryAccess(Operand *Op) {
   return isVariableWithoutRegister(Op) || llvm::isa<OperandARM32Mem>(Op);
 }
+
+bool isMoveBetweenCoreAndVFPRegisters(Variable *Dest, Operand *Src) {
+  const Type DestTy = Dest->getType();
+  const Type SrcTy = Src->getType();
+  assert(isScalarIntegerType(DestTy) + isScalarIntegerType(SrcTy) <= 1 &&

[Jim Stichnoth, 2015/09/18 19:28:55]

Adding bool types?  Ick.  Can you just !(A&&B) ?

[John, 2015/09/18 22:55:53]

I prefer adding the bools, but your solution works. Done.

+         "At most one of vmov's operands can be a core register.");
+  return isScalarIntegerType(DestTy) || isScalarIntegerType(SrcTy);
+}
 } // end of anonymous namespace
 
 void InstARM32Vmov::emitSingleDestSingleSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
   if (Dest->hasReg()) {
     Operand *Src0 = getSrc(0);
     const char *ActualOpcode = isMemoryAccess(Src0) ? "vldr" : "vmov";
-    Str << "\t" << ActualOpcode << "\t";
+    // when vmov{c}'ing, we need to emit a width string. Otherwise, the
+    // assembler might be tempted to assume we want a vector vmov{c}, and that
+    // is disallowed because ARM.
+    const char *WidthString =
+        (isMemoryAccess(Src0) || isMoveBetweenCoreAndVFPRegisters(Dest, Src0))
+            ? ""
+            : getVecWidthString(Src0->getType());
+    Str << "\t" << ActualOpcode << getPredicate() << WidthString << "\t";
     Dest->emit(Func);
     Str << ", ";
     Src0->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
     Str << "\t"
-           "vstr"
-           "\t";
+           "vstr" << getPredicate() << "\t";
     Src0->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   }
 }
 
 void InstARM32Vmov::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  assert(CondARM32::AL == getPredicate());
   assert(isMultiDest() + isMultiSource() <= 1 && "Invalid vmov type.");
   if (isMultiDest()) {
     emitMultiDestSingleSource(Func);
     return;
   }
 
   if (isMultiSource()) {
     emitSingleDestMultiSource(Func);
     return;
   }
@@ skipping 446 matching lines @@
 void InstARM32Vcvt::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = "
       << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << " ";
   dumpSources(Func);
 }
 
+void InstARM32Vcmp::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 2);
+  Str << "\t"
+         "vcmp" << getPredicate() << getVecWidthString(getSrc(0)->getType())
+      << "\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
+  getSrc(1)->emit(Func);
+}
+
+void InstARM32Vcmp::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 2);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Vcmp::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Str << "vcmp" << getPredicate() << getVecWidthString(getSrc(0)->getType());
+  dumpSources(Func);
+}
+
+void InstARM32Vmrs::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 0);
+  Str << "\t"
+         "vmrs" << getPredicate() << "\t"
+                                     "APSR_nzcv"
+                                     ", "
+                                     "FPSCR";
+}
+
+void InstARM32Vmrs::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 0);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Vmrs::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Str << "APSR{n,z,v,c} = vmrs" << getPredicate() << "\t"
+                                                     "FPSCR{n,z,c,v}";
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
     Str << "], ";
@@ skipping 96 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice