Subzero. ARM32 Fcmp lowering.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 383 matching lines @@
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vcvt::create(Func, Dest, Src, Variant, Pred));
   }
   void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vdiv::create(Func, Dest, Src0, Src1));
   }
   void _vldr(Variable *Dest, OperandARM32Mem *Src,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vldr::create(Func, Dest, Src, Pred));
   }
+  void _vcmp(Variable *Src0, Variable *Src1,
+             CondARM32::Cond Pred = CondARM32::AL) {
+    Context.insert(InstARM32Vcmp::create(Func, Src0, Src1, Pred));
+  }
+  void _vmrs(CondARM32::Cond Pred = CondARM32::AL) {
+    Context.insert(InstARM32Vmrs::create(Func, Pred));
+  }
   // There are a whole bunch of vmov variants, to transfer within S/D/Q
   // registers, between core integer registers and S/D, and from small
   // immediates into S/D. For integer -> S/D/Q there is a variant which takes
   // two integer register to fill a D, or to fill two consecutive S registers.
   // Vmov can also be used to insert-element. E.g.,
   //    "vmov.8 d0[1], r0"
   // but insert-element is a "two-address" operation where only part of the
   // register is modified. This cannot model that.
   //
   // This represents the simple single source, single dest variants only.
-  void _vmov(Variable *Dest, Operand *Src0) {
-    constexpr CondARM32::Cond Pred = CondARM32::AL;
+  void _vmov(Variable *Dest, Operand *Src0,
+             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vmov::create(Func, Dest, Src0, Pred));
   }
   // This represents the single source, multi dest variant.
   void _vmov(InstARM32Vmov::RegisterPair Dests, Variable *Src0) {
     constexpr CondARM32::Cond Pred = CondARM32::AL;
     Context.insert(InstARM32Vmov::create(Func, Dests, Src0, Pred));
     // The Vmov instruction created above does not define Dests._1. Therefore
     // we add a Dest._1 = FakeDef pseudo instruction.
     Context.insert(InstFakeDef::create(Func, Dests._1));
   }
@@ skipping 126 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H