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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 426 // feel free to change this if needed.) | 426 // feel free to change this if needed.) |
| 427 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. | 427 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. |
| 428 enum CpuFeature { SSE4_1 = 32 + 19, // x86 | 428 enum CpuFeature { SSE4_1 = 32 + 19, // x86 |
| 429 SSE3 = 32 + 0, // x86 | 429 SSE3 = 32 + 0, // x86 |
| 430 SSE2 = 26, // x86 | 430 SSE2 = 26, // x86 |
| 431 CMOV = 15, // x86 | 431 CMOV = 15, // x86 |
| 432 RDTSC = 4, // x86 | 432 RDTSC = 4, // x86 |
| 433 CPUID = 10, // x86 | 433 CPUID = 10, // x86 |
| 434 VFP3 = 1, // ARM | 434 VFP3 = 1, // ARM |
| 435 ARMv7 = 2, // ARM | 435 ARMv7 = 2, // ARM |
| 436 VFP2 = 3, // ARM | 436 SUDIV = 3, // ARM |
| 437 SUDIV = 4, // ARM | 437 UNALIGNED_ACCESSES = 4, // ARM |
| 438 UNALIGNED_ACCESSES = 5, // ARM | 438 MOVW_MOVT_IMMEDIATE_LOADS = 5, // ARM |
| 439 MOVW_MOVT_IMMEDIATE_LOADS = 6, // ARM | 439 VFP32DREGS = 6, // ARM |
| 440 VFP32DREGS = 7, // ARM | |
| 441 SAHF = 0, // x86 | 440 SAHF = 0, // x86 |
| 442 FPU = 1}; // MIPS | 441 FPU = 1}; // MIPS |
| 443 | 442 |
| 444 | 443 |
| 445 // Used to specify if a macro instruction must perform a smi check on tagged | 444 // Used to specify if a macro instruction must perform a smi check on tagged |
| 446 // values. | 445 // values. |
| 447 enum SmiCheckType { | 446 enum SmiCheckType { |
| 448 DONT_DO_SMI_CHECK, | 447 DONT_DO_SMI_CHECK, |
| 449 DO_SMI_CHECK | 448 DO_SMI_CHECK |
| 450 }; | 449 }; |
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| 572 | 571 |
| 573 enum ClearExceptionFlag { | 572 enum ClearExceptionFlag { |
| 574 KEEP_EXCEPTION, | 573 KEEP_EXCEPTION, |
| 575 CLEAR_EXCEPTION | 574 CLEAR_EXCEPTION |
| 576 }; | 575 }; |
| 577 | 576 |
| 578 | 577 |
| 579 } } // namespace v8::internal | 578 } } // namespace v8::internal |
| 580 | 579 |
| 581 #endif // V8_V8GLOBALS_H_ | 580 #endif // V8_V8GLOBALS_H_ |
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