Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(288)

Side by Side Diff: src/IceTargetLoweringX86BaseImpl.h

Issue 1353923004: Subzero: Fix a couple of debugging tools. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Prepare test for enabling other targets Created 5 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/IceTargetLoweringMIPS32.cpp ('k') | tests_lit/llvm2ice_tests/asm-verbose.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 702 matching lines...) Expand 10 before | Expand all | Expand 10 after
713 if (Ty == IceType_void) 713 if (Ty == IceType_void)
714 Ty = IceType_i32; 714 Ty = IceType_i32;
715 if (PhysicalRegisters[Ty].empty()) 715 if (PhysicalRegisters[Ty].empty())
716 PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM); 716 PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
717 assert(RegNum < PhysicalRegisters[Ty].size()); 717 assert(RegNum < PhysicalRegisters[Ty].size());
718 Variable *Reg = PhysicalRegisters[Ty][RegNum]; 718 Variable *Reg = PhysicalRegisters[Ty][RegNum];
719 if (Reg == nullptr) { 719 if (Reg == nullptr) {
720 Reg = Func->makeVariable(Ty); 720 Reg = Func->makeVariable(Ty);
721 Reg->setRegNum(RegNum); 721 Reg->setRegNum(RegNum);
722 PhysicalRegisters[Ty][RegNum] = Reg; 722 PhysicalRegisters[Ty][RegNum] = Reg;
723 // Specially mark esp as an "argument" so that it is considered live upon 723 // Specially mark a named physical register as an "argument" so that it is
724 // function entry. 724 // considered live upon function entry. Otherwise it's possible to get
725 if (RegNum == Traits::RegisterSet::Reg_esp) { 725 // liveness validation errors for saving callee-save registers.
726 Func->addImplicitArg(Reg); 726 Func->addImplicitArg(Reg);
727 Reg->setIgnoreLiveness(); 727 // Don't bother tracking the live range of a named physical register.
728 } 728 Reg->setIgnoreLiveness();
729 } 729 }
730 return Reg; 730 return Reg;
731 } 731 }
732 732
733 template <class Machine> 733 template <class Machine>
734 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const { 734 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
735 return Traits::getRegName(RegNum, Ty); 735 return Traits::getRegName(RegNum, Ty);
736 } 736 }
737 737
738 template <class Machine> 738 template <class Machine>
(...skipping 4655 matching lines...) Expand 10 before | Expand all | Expand 10 after
5394 } 5394 }
5395 // the offset is not eligible for blinding or pooling, return the original 5395 // the offset is not eligible for blinding or pooling, return the original
5396 // mem operand 5396 // mem operand
5397 return MemOperand; 5397 return MemOperand;
5398 } 5398 }
5399 5399
5400 } // end of namespace X86Internal 5400 } // end of namespace X86Internal
5401 } // end of namespace Ice 5401 } // end of namespace Ice
5402 5402
5403 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H 5403 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
OLDNEW
« no previous file with comments | « src/IceTargetLoweringMIPS32.cpp ('k') | tests_lit/llvm2ice_tests/asm-verbose.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698