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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1353923004: Subzero: Fix a couple of debugging tools. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Prepare test for enabling other targets Created 5 years, 3 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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382 if (Ty == IceType_void) 382 if (Ty == IceType_void)
383 Ty = IceType_i32; 383 Ty = IceType_i32;
384 if (PhysicalRegisters[Ty].empty()) 384 if (PhysicalRegisters[Ty].empty())
385 PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM); 385 PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM);
386 assert(RegNum < PhysicalRegisters[Ty].size()); 386 assert(RegNum < PhysicalRegisters[Ty].size());
387 Variable *Reg = PhysicalRegisters[Ty][RegNum]; 387 Variable *Reg = PhysicalRegisters[Ty][RegNum];
388 if (Reg == nullptr) { 388 if (Reg == nullptr) {
389 Reg = Func->makeVariable(Ty); 389 Reg = Func->makeVariable(Ty);
390 Reg->setRegNum(RegNum); 390 Reg->setRegNum(RegNum);
391 PhysicalRegisters[Ty][RegNum] = Reg; 391 PhysicalRegisters[Ty][RegNum] = Reg;
392 // Specially mark SP and LR as an "argument" so that it is considered live 392 // Specially mark a named physical register as an "argument" so that it is
393 // upon function entry. 393 // considered live upon function entry. Otherwise it's possible to get
394 if (RegNum == RegARM32::Reg_sp || RegNum == RegARM32::Reg_lr) { 394 // liveness validation errors for saving callee-save registers.
395 Func->addImplicitArg(Reg); 395 Func->addImplicitArg(Reg);
396 Reg->setIgnoreLiveness(); 396 // Don't bother tracking the live range of a named physical register.
397 } 397 Reg->setIgnoreLiveness();
398 } 398 }
399 return Reg; 399 return Reg;
400 } 400 }
401 401
402 void TargetARM32::emitJumpTable(const Cfg *Func, 402 void TargetARM32::emitJumpTable(const Cfg *Func,
403 const InstJumpTable *JumpTable) const { 403 const InstJumpTable *JumpTable) const {
404 (void)JumpTable; 404 (void)JumpTable;
405 UnimplementedError(Func->getContext()->getFlags()); 405 UnimplementedError(Func->getContext()->getFlags());
406 } 406 }
407 407
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3203 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; 3203 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n";
3204 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { 3204 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
3205 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; 3205 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n";
3206 } 3206 }
3207 // Technically R9 is used for TLS with Sandboxing, and we reserve it. 3207 // Technically R9 is used for TLS with Sandboxing, and we reserve it.
3208 // However, for compatibility with current NaCl LLVM, don't claim that. 3208 // However, for compatibility with current NaCl LLVM, don't claim that.
3209 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 3209 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
3210 } 3210 }
3211 3211
3212 } // end of namespace Ice 3212 } // end of namespace Ice
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