Improve use of CfgLocalAllocator and introduce containers that use it.

src/IceRegAlloc.h

 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 21 matching lines @@
   explicit LinearScan(Cfg *Func);
   void init(RegAllocKind Kind);
   void scan(const llvm::SmallBitVector &RegMask, bool Randomized);
   void dump(Cfg *Func) const;
 
   // TODO(stichnot): Statically choose the size based on the target being
   // compiled.
   static constexpr size_t REGS_SIZE = 32;
 
 private:
-  using OrderedRanges = std::vector<Variable *>;
-  using UnorderedRanges = std::vector<Variable *>;
+  using OrderedRanges = CfgVector<Variable *>;
+  using UnorderedRanges = CfgVector<Variable *>;
 
   class IterationState {
     IterationState(const IterationState &) = delete;
     IterationState operator=(const IterationState &) = delete;
 
   public:
     IterationState() = default;
     Variable *Cur = nullptr;
     Variable *Prefer = nullptr;
     int32_t PreferReg = Variable::NoRegister;
@@ skipping 42 matching lines @@
 
   Cfg *const Func;
   GlobalContext *const Ctx;
   TargetLowering *const Target;
 
   OrderedRanges Unhandled;
   /// UnhandledPrecolored is a subset of Unhandled, specially collected for
   /// faster processing.
   OrderedRanges UnhandledPrecolored;
   UnorderedRanges Active, Inactive, Handled;
-  std::vector<InstNumberT> Kills;
+  CfgVector<InstNumberT> Kills;
   RegAllocKind Kind = RAK_Unknown;
   /// RegUses[I] is the number of live ranges (variables) that register I is
   /// currently assigned to. It can be greater than 1 as a result of
   /// AllowOverlap inference.
   llvm::SmallVector<int32_t, REGS_SIZE> RegUses;
   // TODO(jpp): for some architectures a SmallBitVector might not be big
   // enough. Evaluate what the performance impact on those architectures is.
   llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases;
   bool FindPreference = false;
   bool FindOverlap = false;
 
   const bool Verbose;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGALLOC_H