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| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 | 5 |
| 6 // Declares a Simulator for MIPS instructions if we are not generating a native | 6 // Declares a Simulator for MIPS instructions if we are not generating a native |
| 7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation | 7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation |
| 8 // on regular desktop machines. | 8 // on regular desktop machines. |
| 9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, | 9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, |
| 10 // which will start execution in the Simulator or forwards to the real entry | 10 // which will start execution in the Simulator or forwards to the real entry |
| (...skipping 95 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 106 char* CachedData(int offset) { | 106 char* CachedData(int offset) { |
| 107 return &data_[offset]; | 107 return &data_[offset]; |
| 108 } | 108 } |
| 109 | 109 |
| 110 private: | 110 private: |
| 111 char data_[kPageSize]; // The cached data. | 111 char data_[kPageSize]; // The cached data. |
| 112 static const int kValidityMapSize = kPageSize >> kLineShift; | 112 static const int kValidityMapSize = kPageSize >> kLineShift; |
| 113 char validity_map_[kValidityMapSize]; // One byte per line. | 113 char validity_map_[kValidityMapSize]; // One byte per line. |
| 114 }; | 114 }; |
| 115 | 115 |
| 116 class SimInstructionBase : public InstructionBase { | |
| 117 public: | |
| 118 Type InstructionType() const { return type_; } | |
| 119 inline Instruction* instr() const { return instr_; } | |
| 120 inline int32_t operand() const { return operand_; } | |
| 121 | |
| 122 protected: | |
| 123 SimInstructionBase() : operand_(-1), instr_(nullptr), type_(kUnsupported) {} | |
| 124 explicit SimInstructionBase(Instruction* instr) {} | |
| 125 | |
| 126 int32_t operand_; | |
| 127 Instruction* instr_; | |
| 128 Type type_; | |
| 129 | |
| 130 private: | |
| 131 DISALLOW_ASSIGN(SimInstructionBase); | |
| 132 }; | |
| 133 | |
| 134 class SimInstruction : public InstructionGetters<SimInstructionBase> { | |
| 135 public: | |
| 136 SimInstruction() {} | |
| 137 | |
| 138 explicit SimInstruction(Instruction* instr) { *this = instr; } | |
| 139 | |
| 140 SimInstruction& operator=(Instruction* instr) { | |
| 141 operand_ = *reinterpret_cast<const int32_t*>(instr); | |
| 142 instr_ = instr; | |
| 143 type_ = InstructionBase::InstructionType(EXTRA); | |
| 144 DCHECK(reinterpret_cast<void*>(&operand_) == this); | |
| 145 return *this; | |
| 146 } | |
| 147 }; | |
| 148 | |
| 116 class Simulator { | 149 class Simulator { |
| 117 public: | 150 public: |
| 118 friend class MipsDebugger; | 151 friend class MipsDebugger; |
| 119 | 152 |
| 120 // Registers are declared in order. See SMRL chapter 2. | 153 // Registers are declared in order. See SMRL chapter 2. |
| 121 enum Register { | 154 enum Register { |
| 122 no_reg = -1, | 155 no_reg = -1, |
| 123 zero_reg = 0, | 156 zero_reg = 0, |
| 124 at, | 157 at, |
| 125 v0, v1, | 158 v0, v1, |
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| 292 EmbeddedVector<char, 128> trace_buf_; | 325 EmbeddedVector<char, 128> trace_buf_; |
| 293 | 326 |
| 294 // Operations depending on endianness. | 327 // Operations depending on endianness. |
| 295 // Get Double Higher / Lower word. | 328 // Get Double Higher / Lower word. |
| 296 inline int32_t GetDoubleHIW(double* addr); | 329 inline int32_t GetDoubleHIW(double* addr); |
| 297 inline int32_t GetDoubleLOW(double* addr); | 330 inline int32_t GetDoubleLOW(double* addr); |
| 298 // Set Double Higher / Lower word. | 331 // Set Double Higher / Lower word. |
| 299 inline int32_t SetDoubleHIW(double* addr); | 332 inline int32_t SetDoubleHIW(double* addr); |
| 300 inline int32_t SetDoubleLOW(double* addr); | 333 inline int32_t SetDoubleLOW(double* addr); |
| 301 | 334 |
| 335 SimInstruction instr_; | |
| 336 | |
| 302 // Executing is handled based on the instruction type. | 337 // Executing is handled based on the instruction type. |
| 303 void DecodeTypeRegister(Instruction* instr); | 338 void DecodeTypeRegister(); |
| 304 | 339 |
| 305 // Functions called from DecodeTypeRegister. | 340 // Functions called from DecodeTypeRegister. |
| 306 void DecodeTypeRegisterCOP1(); | 341 void DecodeTypeRegisterCOP1(); |
| 307 | 342 |
| 308 void DecodeTypeRegisterCOP1X(); | 343 void DecodeTypeRegisterCOP1X(); |
| 309 | 344 |
| 310 void DecodeTypeRegisterSPECIAL(); | 345 void DecodeTypeRegisterSPECIAL(); |
| 311 | 346 |
| 312 void DecodeTypeRegisterSPECIAL2(); | 347 void DecodeTypeRegisterSPECIAL2(); |
| 313 | 348 |
| 314 void DecodeTypeRegisterSPECIAL3(); | 349 void DecodeTypeRegisterSPECIAL3(); |
| 315 | 350 |
| 316 // Called from DecodeTypeRegisterCOP1. | 351 // Called from DecodeTypeRegisterCOP1. |
| 317 void DecodeTypeRegisterSRsType(); | 352 void DecodeTypeRegisterSRsType(); |
| 318 | 353 |
| 319 void DecodeTypeRegisterDRsType(); | 354 void DecodeTypeRegisterDRsType(); |
| 320 | 355 |
| 321 void DecodeTypeRegisterWRsType(); | 356 void DecodeTypeRegisterWRsType(); |
| 322 | 357 |
| 323 void DecodeTypeRegisterLRsType(); | 358 void DecodeTypeRegisterLRsType(); |
| 324 | 359 |
| 325 Instruction* currentInstr_; | 360 // inline Instruction* get_instr() const { return instr_.instr(); } |
|
miran.karic
2016/09/22 12:24:06
Is there a reason to keep these commented out func
balazs.kilvady
2016/09/22 16:46:09
Done.
| |
| 361 // inline void set_instr(Instruction* instr) { instr_ = instr; } | |
| 326 | 362 |
| 327 inline Instruction* get_instr() const { return currentInstr_; } | 363 inline int32_t rs_reg() const { return instr_.RsValue(); } |
| 328 inline void set_instr(Instruction* instr) { currentInstr_ = instr; } | |
| 329 | |
| 330 inline int32_t rs_reg() const { return currentInstr_->RsValue(); } | |
| 331 inline int32_t rs() const { return get_register(rs_reg()); } | 364 inline int32_t rs() const { return get_register(rs_reg()); } |
| 332 inline uint32_t rs_u() const { | 365 inline uint32_t rs_u() const { |
| 333 return static_cast<uint32_t>(get_register(rs_reg())); | 366 return static_cast<uint32_t>(get_register(rs_reg())); |
| 334 } | 367 } |
| 335 inline int32_t rt_reg() const { return currentInstr_->RtValue(); } | 368 inline int32_t rt_reg() const { return instr_.RtValue(); } |
| 336 inline int32_t rt() const { return get_register(rt_reg()); } | 369 inline int32_t rt() const { return get_register(rt_reg()); } |
| 337 inline uint32_t rt_u() const { | 370 inline uint32_t rt_u() const { |
| 338 return static_cast<uint32_t>(get_register(rt_reg())); | 371 return static_cast<uint32_t>(get_register(rt_reg())); |
| 339 } | 372 } |
| 340 inline int32_t rd_reg() const { return currentInstr_->RdValue(); } | 373 inline int32_t rd_reg() const { return instr_.RdValue(); } |
| 341 inline int32_t fr_reg() const { return currentInstr_->FrValue(); } | 374 inline int32_t fr_reg() const { return instr_.FrValue(); } |
| 342 inline int32_t fs_reg() const { return currentInstr_->FsValue(); } | 375 inline int32_t fs_reg() const { return instr_.FsValue(); } |
| 343 inline int32_t ft_reg() const { return currentInstr_->FtValue(); } | 376 inline int32_t ft_reg() const { return instr_.FtValue(); } |
| 344 inline int32_t fd_reg() const { return currentInstr_->FdValue(); } | 377 inline int32_t fd_reg() const { return instr_.FdValue(); } |
| 345 inline int32_t sa() const { return currentInstr_->SaValue(); } | 378 inline int32_t sa() const { return instr_.SaValue(); } |
| 346 inline int32_t lsa_sa() const { return currentInstr_->LsaSaValue(); } | 379 inline int32_t lsa_sa() const { return instr_.LsaSaValue(); } |
| 347 | 380 |
| 348 inline void SetResult(int32_t rd_reg, int32_t alu_out) { | 381 inline void SetResult(int32_t rd_reg, int32_t alu_out) { |
| 349 set_register(rd_reg, alu_out); | 382 set_register(rd_reg, alu_out); |
| 350 TraceRegWr(alu_out); | 383 TraceRegWr(alu_out); |
| 351 } | 384 } |
| 352 | 385 |
| 353 void DecodeTypeImmediate(Instruction* instr); | 386 void DecodeTypeImmediate(); |
| 354 void DecodeTypeJump(Instruction* instr); | 387 void DecodeTypeJump(); |
| 355 | 388 |
| 356 // Used for breakpoints and traps. | 389 // Used for breakpoints and traps. |
| 357 void SoftwareInterrupt(Instruction* instr); | 390 void SoftwareInterrupt(); |
| 358 | 391 |
| 359 // Compact branch guard. | 392 // Compact branch guard. |
| 360 void CheckForbiddenSlot(int32_t current_pc) { | 393 void CheckForbiddenSlot(int32_t current_pc) { |
| 361 Instruction* instr_after_compact_branch = | 394 Instruction* instr_after_compact_branch = |
| 362 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); | 395 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); |
| 363 if (instr_after_compact_branch->IsForbiddenAfterBranch()) { | 396 if (instr_after_compact_branch->IsForbiddenAfterBranch()) { |
| 364 V8_Fatal(__FILE__, __LINE__, | 397 V8_Fatal(__FILE__, __LINE__, |
| 365 "Error: Unexpected instruction 0x%08x immediately after a " | 398 "Error: Unexpected instruction 0x%08x immediately after a " |
| 366 "compact branch instruction.", | 399 "compact branch instruction.", |
| 367 *reinterpret_cast<uint32_t*>(instr_after_compact_branch)); | 400 *reinterpret_cast<uint32_t*>(instr_after_compact_branch)); |
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| 503 static inline void UnregisterCTryCatch(Isolate* isolate) { | 536 static inline void UnregisterCTryCatch(Isolate* isolate) { |
| 504 Simulator::current(isolate)->PopAddress(); | 537 Simulator::current(isolate)->PopAddress(); |
| 505 } | 538 } |
| 506 }; | 539 }; |
| 507 | 540 |
| 508 } // namespace internal | 541 } // namespace internal |
| 509 } // namespace v8 | 542 } // namespace v8 |
| 510 | 543 |
| 511 #endif // !defined(USE_SIMULATOR) | 544 #endif // !defined(USE_SIMULATOR) |
| 512 #endif // V8_MIPS_SIMULATOR_MIPS_H_ | 545 #endif // V8_MIPS_SIMULATOR_MIPS_H_ |
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