Introduces a second temporary register for MIPS assembler macros.

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
===================================================================
--- runtime/vm/assembler_mips.h	(revision 21085)
+++ runtime/vm/assembler_mips.h	(working copy)
@@ -58,13 +58,13 @@
   }
 
   uint32_t encoding() const {
-    ASSERT(Utils::IsInt(16, offset_));
+    ASSERT(Utils::IsInt(kImmBits, offset_));
     uint16_t imm_value = static_cast<uint16_t>(offset_);
     return (base_ << kRsShift) | imm_value;
   }
 
   static bool CanHoldOffset(int32_t offset) {
-    return Utils::IsInt(16, offset);
+    return Utils::IsInt(kImmBits, offset);
   }
 
  private:
@@ -224,7 +224,7 @@
 
   // CPU instructions in alphabetical order.
   void addiu(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsInt(16, imm.value()));
+    ASSERT(Utils::IsInt(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
@@ -238,7 +238,7 @@
   }
 
   void andi(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ANDI, rs, rt, imm_value);
   }
@@ -397,7 +397,7 @@
   }
 
   void lui(Register rt, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
@@ -447,7 +447,7 @@
   }
 
   void ori(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
@@ -508,51 +508,45 @@
 
   // Addition of rs and rt with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
-  // A scratch register is needed when rd, rs, and rt are the same
-  // register. The scratch register may not be TMP.
+  // rd and ro must not be TMP1 or TMP2.
   // ro must be different from all the other registers.
-  void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro,
-                          Register scratch = kNoRegister);
+  void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro);
 
+  // ro must be different from rd and rs.
+  // rd and ro must not be TMP1 or TMP2
+  void AddImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
+                                  Register ro) {
+    LoadImmediate(rd, imm);
+    AdduDetectOverflow(rd, rs, rd, ro);
+  }
+
   void Branch(const ExternalLabel* label) {
-    LoadImmediate(TMP, label->address());
-    jr(TMP);
+    LoadImmediate(TMP1, label->address());
+    jr(TMP1);
   }
 
   void BranchPatchable(const ExternalLabel* label) {
     const uint16_t low = Utils::Low16Bits(label->address());
     const uint16_t high = Utils::High16Bits(label->address());
-    lui(TMP, Immediate(high));
-    ori(TMP, TMP, Immediate(low));
-    jr(TMP);
+    lui(TMP1, Immediate(high));
+    ori(TMP1, TMP1, Immediate(low));
+    jr(TMP1);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
   void BranchLink(const ExternalLabel* label) {
-    LoadImmediate(TMP, label->address());
-    jalr(TMP);
+    LoadImmediate(TMP1, label->address());
+    jalr(TMP1);
   }
 
   void BranchLinkPatchable(const ExternalLabel* label) {
     const int32_t offset =
         Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
-    LoadWordFromPoolOffset(TMP, offset);
-    jalr(TMP);
+    LoadWordFromPoolOffset(TMP1, offset);
+    jalr(TMP1);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
-  // If the signed value in rs is less than value, rd is 1, and 0 otherwise.
-  void LessThanSImmediate(Register rd, Register rs, int32_t value) {
-    LoadImmediate(TMP, value);
-    slt(rd, rs, TMP);
-  }
-
-  // If the unsigned value in rs is less than value, rd is 1, and 0 otherwise.
-  void LessThanUImmediate(Register rd, Register rs, uint32_t value) {
-    LoadImmediate(TMP, value);
-    sltu(rd, rs, TMP);
-  }
-
   void Drop(intptr_t stack_elements) {
     ASSERT(stack_elements >= 0);
     if (stack_elements > 0) {
@@ -561,7 +555,7 @@
   }
 
   void LoadImmediate(Register rd, int32_t value) {
-    if (Utils::IsInt(16, value)) {
+    if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       const uint16_t low = Utils::Low16Bits(value);
@@ -571,6 +565,90 @@
     }
   }
 
+  void BranchEq(Register rd, int32_t value, Label* l) {

[regis, 2013/04/08 21:41:18]

We usually spell out the name in macros:
BranchEqual
BranchNotEqual
BranchGreater
etc

[zra, 2013/04/08 22:04:12]

Done.

+    LoadImmediate(TMP1, value);
+    beq(rd, TMP1, l);
+  }
+
+  void BranchEq(Register rd, const Object& object, Label* l) {
+    LoadObject(TMP1, object);
+    beq(rd, TMP1, l);
+  }
+
+  void BranchNe(Register rd, int32_t value, Label* l) {
+    LoadImmediate(TMP1, value);
+    bne(rd, TMP1, l);
+  }
+
+  void BranchNe(Register rd, const Object& object, Label* l) {
+    LoadObject(TMP1, object);
+    bne(rd, TMP1, l);
+  }
+
+  void BranchGt(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bgtz(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bgtz(TMP1, l);
+    }
+  }
+
+  void BranchGt(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bgtz(TMP1, l);
+  }
+
+  void BranchGe(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bgez(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bgez(TMP1, l);
+    }
+  }
+
+  void BranchGe(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bgez(TMP1, l);
+  }
+
+  void BranchLt(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bltz(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bltz(TMP1, l);
+    }
+  }
+
+  void BranchLt(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bltz(TMP1, l);
+  }
+
+  void BranchLe(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      blez(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      blez(TMP1, l);
+    }
+  }
+
+  void BranchLe(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    blez(TMP1, l);
+  }
+
   void Push(Register rt) {
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
@@ -605,7 +683,7 @@
 
   void LoadClassId(Register result, Register object);
   void LoadClassById(Register result, Register class_id);
-  void LoadClass(Register result, Register object, Register scratch);
+  void LoadClass(Register result, Register object);
 
   void CallRuntime(const RuntimeEntry& entry);