Introduces a second temporary register for MIPS assembler macros.

runtime/vm/flow_graph_compiler_mips.cc

Index: runtime/vm/flow_graph_compiler_mips.cc
===================================================================
--- runtime/vm/flow_graph_compiler_mips.cc	(revision 20999)
+++ runtime/vm/flow_graph_compiler_mips.cc	(working copy)
@@ -84,8 +84,7 @@
                                       Label* is_equal_lbl,
                                       Label* is_not_equal_lbl) {
   for (intptr_t i = 0; i < class_ids.length(); i++) {
-    __ LoadImmediate(TMP, class_ids[i]);
-    __ beq(class_id_reg, TMP, is_equal_lbl);
+    __ BranchEqual(class_id_reg, class_ids[i], is_equal_lbl);
   }
   __ b(is_not_equal_lbl);
 }
@@ -121,14 +120,13 @@
   // Compare if the classes are equal.
   const Register kClassIdReg = T0;
   __ LoadClassId(kClassIdReg, kInstanceReg);
-  __ LoadImmediate(T1, type_class.id());
-  __ beq(kClassIdReg, T1, is_instance_lbl);
+  __ BranchEqual(kClassIdReg, type_class.id(), is_instance_lbl);
+
   // See ClassFinalizer::ResolveSuperTypeAndInterfaces for list of restricted
   // interfaces.
   // Bool interface can be implemented only by core class Bool.
   if (type.IsBoolType()) {
-    __ LoadImmediate(T1, kBoolCid);
-    __ beq(kClassIdReg, T1, is_instance_lbl);
+    __ BranchEqual(kClassIdReg, kBoolCid, is_instance_lbl);
     __ b(is_not_instance_lbl);
     return false;
   }
@@ -136,8 +134,8 @@
     // Check if instance is a closure.
     __ LoadClassById(T1, kClassIdReg);
     __ lw(T1, FieldAddress(T1, Class::signature_function_offset()));
-    __ LoadImmediate(T2, reinterpret_cast<int32_t>(Object::null()));
-    __ bne(T1, T2, is_instance_lbl);
+    __ BranchNotEqual(T1, reinterpret_cast<int32_t>(Object::null()),
+                      is_instance_lbl);
   }
   // Custom checking for numbers (Smi, Mint, Bigint and Double).
   // Note that instance is not Smi (checked above).
@@ -204,8 +202,7 @@
     } else {
       __ beq(T0, ZR, is_not_instance_lbl);
       __ LoadClassId(T0, kInstanceReg);
-      __ LoadImmediate(T1, type_cid);
-      __ beq(T0, T1, is_instance_lbl);
+      __ BranchEqual(T0, type_cid, is_instance_lbl);
     }
     __ b(is_not_instance_lbl);
     return SubtypeTestCache::null();
@@ -282,14 +279,12 @@
   __ sw(A1, Address(SP, 0 * kWordSize));
   // A null object is always assignable and is returned as result.
   Label is_assignable, runtime_call;
-  __ LoadImmediate(T0, reinterpret_cast<int32_t>(Object::null()));
-  __ beq(A0, T0, &is_assignable);
+  __ BranchEqual(A0, reinterpret_cast<int32_t>(Object::null()), &is_assignable);
 
   if (!FLAG_eliminate_type_checks) {
     // If type checks are not eliminated during the graph building then
     // a transition sentinel can be seen here.
-    __ LoadObject(T0, Object::transition_sentinel());
-    __ beq(A0, T0, &is_assignable);
+    __ BranchEqual(A0, Object::transition_sentinel(), &is_assignable);
   }
 
   // Generate throw new TypeError() if the type is malformed.
@@ -344,9 +339,9 @@
 
   __ Bind(&is_assignable);
   // Restore instantiator and its type arguments.
-    __ lw(A1, Address(SP, 0 * kWordSize));
-    __ lw(A2, Address(SP, 1 * kWordSize));
-    __ addiu(SP, SP, Immediate(2 * kWordSize));
+  __ lw(A1, Address(SP, 0 * kWordSize));
+  __ lw(A2, Address(SP, 1 * kWordSize));
+  __ addiu(SP, SP, Immediate(2 * kWordSize));
 }
 
 
@@ -394,19 +389,17 @@
   __ lw(T2, FieldAddress(S4, ArgumentsDescriptor::positional_count_offset()));
   // Check that min_num_pos_args <= num_pos_args.
   Label wrong_num_arguments;
-  __ addiu(T3, T2, Immediate(-Smi::RawValue(min_num_pos_args)));
-  __ bltz(T3, &wrong_num_arguments);
+  __ BranchLess(T2, Smi::RawValue(min_num_pos_args), &wrong_num_arguments);
 
   // Check that num_pos_args <= max_num_pos_args.
-  __ addiu(T3, T2, Immediate(-Smi::RawValue(max_num_pos_args)));
-  __ bgtz(T3, &wrong_num_arguments);
+  __ BranchGreater(T2, Smi::RawValue(max_num_pos_args), &wrong_num_arguments);
 
   // Copy positional arguments.
   // Argument i passed at fp[kLastParamSlotIndex + num_args - 1 - i] is copied
   // to fp[kFirstLocalSlotIndex - i].
 
   __ lw(T1, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
-  // Since T1 and T2 are Smi, use LSL 1 instead of LSL 2.
+  // Since T1 and T2 are Smi, use sll 1 instead of sll 2.
   // Let T1 point to the last passed positional argument, i.e. to
   // fp[kLastParamSlotIndex + num_args - 1 - (num_pos_args - 1)].
   __ subu(T1, T1, T2);
@@ -429,8 +422,8 @@
   __ Bind(&loop);
   __ addu(T4, T1, T2);
   __ addu(T5, T0, T2);
-  __ lw(TMP, Address(T4));
-  __ sw(TMP, Address(T5));
+  __ lw(T3, Address(T4));
+  __ sw(T3, Address(T5));
   __ Bind(&loop_condition);
   __ addiu(T2, T2, Immediate(-kWordSize));
   __ bgez(T2, &loop);
@@ -475,8 +468,7 @@
       // Load T3 with the name of the argument.
       __ lw(T3, Address(T0, ArgumentsDescriptor::name_offset()));
       ASSERT(opt_param[i]->name().IsSymbol());
-      __ LoadObject(T4, opt_param[i]->name());
-      __ bne(T3, T4, &load_default_value);
+      __ BranchNotEqual(T3, opt_param[i]->name(), &load_default_value);
 
       // Load T3 with passed-in argument at provided arg_pos, i.e. at
       // fp[kLastParamSlotIndex + num_args - 1 - arg_pos].
@@ -508,8 +500,8 @@
     delete[] opt_param_position;
     // Check that T0 now points to the null terminator in the array descriptor.
     __ lw(T3, Address(T0));
-    __ LoadImmediate(T4, reinterpret_cast<int32_t>(Object::null()));
-    __ beq(T3, T4, &all_arguments_processed);
+    __ BranchEqual(T3, reinterpret_cast<int32_t>(Object::null()),
+                &all_arguments_processed);
   } else {
     ASSERT(num_opt_pos_params > 0);
     __ lw(T2,
@@ -521,8 +513,7 @@
       // arguments have been passed, where k is param_pos, the position of this
       // optional parameter in the formal parameter list.
       const int param_pos = num_fixed_params + i;
-      __ addiu(T3, T2, Immediate(-param_pos));
-      __ bgtz(T3, &next_parameter);
+      __ BranchGreater(T2, param_pos, &next_parameter);
       // Load T3 with default argument.
       const Object& value = Object::ZoneHandle(
           parsed_function().default_parameter_values().At(i));
@@ -538,7 +529,7 @@
     __ lw(T1, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
     __ SmiUntag(T1);
     // Check that T2 equals T1, i.e. no named arguments passed.
-    __ beq(T2, T2, &all_arguments_processed);
+    __ beq(T2, T1, &all_arguments_processed);
   }
 
   __ Bind(&wrong_num_arguments);
@@ -590,13 +581,13 @@
   __ lw(T2, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
   __ SmiUntag(T2);
 
-  __ LoadImmediate(TMP, reinterpret_cast<intptr_t>(Object::null()));
+  __ LoadImmediate(T0, reinterpret_cast<intptr_t>(Object::null()));
   Label null_args_loop, null_args_loop_condition;
   __ b(&null_args_loop_condition);
   __ delay_slot()->addiu(T1, FP, Immediate(kLastParamSlotIndex * kWordSize));
   __ Bind(&null_args_loop);
   __ addu(T3, T1, T2);
-  __ sw(TMP, Address(T3));
+  __ sw(T0, Address(T3));
   __ Bind(&null_args_loop_condition);
   __ addiu(T2, T2, Immediate(-kWordSize));
   __ bgez(T2, &null_args_loop);
@@ -622,7 +613,7 @@
       Label next;
       // The pool pointer is not setup before entering the Dart frame.
 
-      __ mov(TMP, RA);  // Save RA.
+      __ mov(TMP1, RA);  // Save RA.
       __ bal(&next);  // Branch and link to next instruction to get PC in RA.
       __ delay_slot()->mov(T2, RA);  // Save PC of the following mov.
 
@@ -632,7 +623,7 @@
          assembler()->CodeSize();
 
       __ Bind(&next);
-      __ mov(RA, TMP);  // Restore RA.
+      __ mov(RA, TMP1);  // Restore RA.
 
       // Preserve PP of caller.
       __ mov(T1, PP);
@@ -666,9 +657,7 @@
 
       // Skip Branch if T1 is less than the threshold.
       Label dont_branch;
-      __ LoadImmediate(T2, FLAG_optimization_counter_threshold);
-      __ sltu(T2, T1, T2);
-      __ bgtz(T2, &dont_branch);
+      __ BranchLess(T1, FLAG_optimization_counter_threshold, &dont_branch);
 
       ASSERT(function_reg == T0);
       __ Branch(&StubCode::OptimizeFunctionLabel());
@@ -729,8 +718,8 @@
       // Check that exactly num_fixed arguments are passed in.
       Label correct_num_arguments, wrong_num_arguments;
       __ lw(T0, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
-      __ LoadImmediate(T1, Smi::RawValue(num_fixed_params));
-      __ bne(T0, T1, &wrong_num_arguments);
+      __ BranchNotEqual(T0, Smi::RawValue(num_fixed_params),
+                        &wrong_num_arguments);
 
       __ lw(T1, FieldAddress(S4,
                              ArgumentsDescriptor::positional_count_offset()));