Introduces a second temporary register for MIPS assembler macros.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 40 matching lines @@
 
   Address(const Address& other)
       : ValueObject(), base_(other.base_), offset_(other.offset_) { }
   Address& operator=(const Address& other) {
     base_ = other.base_;
     offset_ = other.offset_;
     return *this;
   }
 
   uint32_t encoding() const {
-    ASSERT(Utils::IsInt(16, offset_));
+    ASSERT(Utils::IsInt(kImmBits, offset_));
     uint16_t imm_value = static_cast<uint16_t>(offset_);
     return (base_ << kRsShift) | imm_value;
   }
 
   static bool CanHoldOffset(int32_t offset) {
-    return Utils::IsInt(16, offset);
+    return Utils::IsInt(kImmBits, offset);
   }
 
  private:
   Register base_;
   int32_t offset_;
 };
 
 
 class FieldAddress : public Address {
  public:
@@ skipping 139 matching lines @@
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
         Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions in alphabetical order.
   void addiu(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsInt(16, imm.value()));
+    ASSERT(Utils::IsInt(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
 
   void addu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, ADDU);
   }
 
   void and_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
   }
 
   void andi(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ANDI, rs, rt, imm_value);
   }
 
   // Unconditional branch.
   void b(Label* l) {
     beq(R0, R0, l);
   }
 
   void bal(Label *l) {
@@ skipping 138 matching lines @@
 
   void lh(Register rt, const Address& addr) {
     EmitLoadStore(LH, rt, addr);
   }
 
   void lhu(Register rt, const Address& addr) {
     EmitLoadStore(LHU, rt, addr);
   }
 
   void lui(Register rt, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
   void lw(Register rt, const Address& addr) {
     EmitLoadStore(LW, rt, addr);
   }
 
   void mfhi(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
@@ skipping 29 matching lines @@
 
   void nor(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, NOR);
   }
 
   void or_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, OR);
   }
 
   void ori(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void sb(Register rt, const Address& addr) {
     EmitLoadStore(SB, rt, addr);
   }
 
   void sh(Register rt, const Address& addr) {
     EmitLoadStore(SH, rt, addr);
@@ skipping 40 matching lines @@
   }
 
   void xor_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, XOR);
   }
 
   // Macros in alphabetical order.
 
   // Addition of rs and rt with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
-  // A scratch register is needed when rd, rs, and rt are the same
-  // register. The scratch register may not be TMP.
+  // rd and ro must not be TMP1 or TMP2.
   // ro must be different from all the other registers.
-  void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro,
-                          Register scratch = kNoRegister);
+  void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro);
+
+  // ro must be different from rd and rs.
+  // rd and ro must not be TMP1 or TMP2
+  void AddImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
+                                  Register ro) {
+    LoadImmediate(rd, imm);
+    AdduDetectOverflow(rd, rs, rd, ro);
+  }
 
   void Branch(const ExternalLabel* label) {
-    LoadImmediate(TMP, label->address());
-    jr(TMP);
+    LoadImmediate(TMP1, label->address());
+    jr(TMP1);
   }
 
   void BranchPatchable(const ExternalLabel* label) {
     const uint16_t low = Utils::Low16Bits(label->address());
     const uint16_t high = Utils::High16Bits(label->address());
-    lui(TMP, Immediate(high));
-    ori(TMP, TMP, Immediate(low));
-    jr(TMP);
+    lui(TMP1, Immediate(high));
+    ori(TMP1, TMP1, Immediate(low));
+    jr(TMP1);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
   void BranchLink(const ExternalLabel* label) {
-    LoadImmediate(TMP, label->address());
-    jalr(TMP);
+    LoadImmediate(TMP1, label->address());
+    jalr(TMP1);
   }
 
   void BranchLinkPatchable(const ExternalLabel* label) {
     const int32_t offset =
         Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
-    LoadWordFromPoolOffset(TMP, offset);
-    jalr(TMP);
+    LoadWordFromPoolOffset(TMP1, offset);
+    jalr(TMP1);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
-  // If the signed value in rs is less than value, rd is 1, and 0 otherwise.
-  void LessThanSImmediate(Register rd, Register rs, int32_t value) {
-    LoadImmediate(TMP, value);
-    slt(rd, rs, TMP);
-  }
-
-  // If the unsigned value in rs is less than value, rd is 1, and 0 otherwise.
-  void LessThanUImmediate(Register rd, Register rs, uint32_t value) {
-    LoadImmediate(TMP, value);
-    sltu(rd, rs, TMP);
-  }
-
   void Drop(intptr_t stack_elements) {
     ASSERT(stack_elements >= 0);
     if (stack_elements > 0) {
       addiu(SP, SP, Immediate(stack_elements * kWordSize));
     }
   }
 
   void LoadImmediate(Register rd, int32_t value) {
-    if (Utils::IsInt(16, value)) {
+    if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       const uint16_t low = Utils::Low16Bits(value);
       const uint16_t high = Utils::High16Bits(value);
       lui(rd, Immediate(high));
       ori(rd, rd, Immediate(low));
     }
   }
 
+  void BranchEqual(Register rd, int32_t value, Label* l) {
+    LoadImmediate(TMP1, value);
+    beq(rd, TMP1, l);
+  }
+
+  void BranchEqual(Register rd, const Object& object, Label* l) {
+    LoadObject(TMP1, object);
+    beq(rd, TMP1, l);
+  }
+
+  void BranchNotEqual(Register rd, int32_t value, Label* l) {
+    LoadImmediate(TMP1, value);
+    bne(rd, TMP1, l);
+  }
+
+  void BranchNotEqual(Register rd, const Object& object, Label* l) {
+    LoadObject(TMP1, object);
+    bne(rd, TMP1, l);
+  }
+
+  void BranchGreater(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bgtz(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bgtz(TMP1, l);
+    }
+  }
+
+  void BranchGreater(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bgtz(TMP1, l);
+  }
+
+  void BranchGreaterEqual(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bgez(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bgez(TMP1, l);
+    }
+  }
+
+  void BranchGreaterEqual(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bgez(TMP1, l);
+  }
+
+  void BranchLess(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      bltz(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      bltz(TMP1, l);
+    }
+  }
+
+  void BranchLess(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    bltz(TMP1, l);
+  }
+
+  void BranchLessEqual(Register rd, int32_t value, Label* l) {
+    if (Utils::IsInt(kImmBits, -value)) {
+      addiu(TMP1, rd, Immediate(-value));
+      blez(TMP1, l);
+    } else {
+      LoadImmediate(TMP1, value);
+      subu(TMP1, rd, TMP1);
+      blez(TMP1, l);
+    }
+  }
+
+  void BranchLessEqual(Register rd, Register rs, Label* l) {
+    subu(TMP1, rd, rs);
+    blez(TMP1, l);
+  }
+
   void Push(Register rt) {
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
     lw(rt, Address(SP));
     addiu(SP, SP, Immediate(kWordSize));
   }
 
@@ skipping 14 matching lines @@
   void LoadWordFromPoolOffset(Register rd, int32_t offset);
   void LoadObject(Register rd, const Object& object);
   void PushObject(const Object& object);
 
   // Sets register rd to zero if the object is equal to register rn,
   // set to non-zero otherwise.
   void CompareObject(Register rd, Register rn, const Object& object);
 
   void LoadClassId(Register result, Register object);
   void LoadClassById(Register result, Register class_id);
-  void LoadClass(Register result, Register object, Register scratch);
+  void LoadClass(Register result, Register object);
 
   void CallRuntime(const RuntimeEntry& entry);
 
   // Set up a Dart frame on entry with a frame pointer and PC information to
   // enable easy access to the RawInstruction object of code corresponding
   // to this frame.
   void EnterDartFrame(intptr_t frame_size);
   void LeaveDartFrame();
 
  private:
@@ skipping 118 matching lines @@
     delay_slot_available_ = true;
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_