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Side by Side Diff: runtime/vm/flow_graph_compiler_ia32.cc

Issue 13471013: Flow graph SIMD changes (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart
Patch Set: Created 7 years, 8 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_IA32. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_IA32.
6 #if defined(TARGET_ARCH_IA32) 6 #if defined(TARGET_ARCH_IA32)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "lib/error.h" 10 #include "lib/error.h"
(...skipping 1575 matching lines...) Expand 10 before | Expand all | Expand 10 after
1586 ASSERT(destination.IsStackSlot()); 1586 ASSERT(destination.IsStackSlot());
1587 MoveMemoryToMemory(destination.ToStackSlotAddress(), 1587 MoveMemoryToMemory(destination.ToStackSlotAddress(),
1588 source.ToStackSlotAddress()); 1588 source.ToStackSlotAddress());
1589 } 1589 }
1590 } else if (source.IsFpuRegister()) { 1590 } else if (source.IsFpuRegister()) {
1591 if (destination.IsFpuRegister()) { 1591 if (destination.IsFpuRegister()) {
1592 // Optimization manual recommends using MOVAPS for register 1592 // Optimization manual recommends using MOVAPS for register
1593 // to register moves. 1593 // to register moves.
1594 __ movaps(destination.fpu_reg(), source.fpu_reg()); 1594 __ movaps(destination.fpu_reg(), source.fpu_reg());
1595 } else { 1595 } else {
1596 ASSERT(destination.IsDoubleStackSlot()); 1596 if (destination.IsDoubleStackSlot()) {
1597 __ movsd(destination.ToStackSlotAddress(), source.fpu_reg()); 1597 __ movsd(destination.ToStackSlotAddress(), source.fpu_reg());
1598 } else {
1599 ASSERT(destination.IsFloat32x4StackSlot() ||
1600 destination.IsUint32x4StackSlot());
1601 __ movups(destination.ToStackSlotAddress(), source.fpu_reg());
1602 }
1598 } 1603 }
1599 } else if (source.IsDoubleStackSlot()) { 1604 } else if (source.IsDoubleStackSlot()) {
1600 if (destination.IsFpuRegister()) { 1605 if (destination.IsFpuRegister()) {
1601 __ movsd(destination.fpu_reg(), source.ToStackSlotAddress()); 1606 __ movsd(destination.fpu_reg(), source.ToStackSlotAddress());
1602 } else { 1607 } else {
1603 ASSERT(destination.IsDoubleStackSlot()); 1608 ASSERT(destination.IsDoubleStackSlot());
1604 __ movsd(XMM0, source.ToStackSlotAddress()); 1609 __ movsd(XMM0, source.ToStackSlotAddress());
1605 __ movsd(destination.ToStackSlotAddress(), XMM0); 1610 __ movsd(destination.ToStackSlotAddress(), XMM0);
1606 } 1611 }
1612 } else if (source.IsFloat32x4StackSlot() || source.IsUint32x4StackSlot()) {
1613 if (destination.IsFpuRegister()) {
1614 __ movups(destination.fpu_reg(), source.ToStackSlotAddress());
1615 } else {
1616 ASSERT(destination.IsFloat32x4StackSlot() ||
1617 destination.IsUint32x4StackSlot());
1618 __ movups(XMM0, source.ToStackSlotAddress());
1619 __ movups(destination.ToStackSlotAddress(), XMM0);
1620 }
1607 } else { 1621 } else {
1608 ASSERT(source.IsConstant()); 1622 ASSERT(source.IsConstant());
1609 if (destination.IsRegister()) { 1623 if (destination.IsRegister()) {
1610 const Object& constant = source.constant(); 1624 const Object& constant = source.constant();
1611 if (constant.IsSmi() && (Smi::Cast(constant).Value() == 0)) { 1625 if (constant.IsSmi() && (Smi::Cast(constant).Value() == 0)) {
1612 __ xorl(destination.reg(), destination.reg()); 1626 __ xorl(destination.reg(), destination.reg());
1613 } else { 1627 } else {
1614 __ LoadObject(destination.reg(), constant); 1628 __ LoadObject(destination.reg(), constant);
1615 } 1629 }
1616 } else { 1630 } else {
(...skipping 17 matching lines...) Expand all
1634 Exchange(source.reg(), destination.ToStackSlotAddress()); 1648 Exchange(source.reg(), destination.ToStackSlotAddress());
1635 } else if (source.IsStackSlot() && destination.IsRegister()) { 1649 } else if (source.IsStackSlot() && destination.IsRegister()) {
1636 Exchange(destination.reg(), source.ToStackSlotAddress()); 1650 Exchange(destination.reg(), source.ToStackSlotAddress());
1637 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1651 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1638 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); 1652 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
1639 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1653 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1640 __ movaps(XMM0, source.fpu_reg()); 1654 __ movaps(XMM0, source.fpu_reg());
1641 __ movaps(source.fpu_reg(), destination.fpu_reg()); 1655 __ movaps(source.fpu_reg(), destination.fpu_reg());
1642 __ movaps(destination.fpu_reg(), XMM0); 1656 __ movaps(destination.fpu_reg(), XMM0);
1643 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1657 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1644 ASSERT(destination.IsDoubleStackSlot() || source.IsDoubleStackSlot()); 1658 ASSERT(destination.IsDoubleStackSlot() ||
1659 destination.IsFloat32x4StackSlot() ||
1660 destination.IsUint32x4StackSlot() ||
1661 source.IsDoubleStackSlot() ||
1662 source.IsFloat32x4StackSlot() ||
1663 source.IsUint32x4StackSlot());
1664 bool double_width = destination.IsDoubleStackSlot() ||
1665 source.IsDoubleStackSlot();
1645 XmmRegister reg = source.IsFpuRegister() ? source.fpu_reg() 1666 XmmRegister reg = source.IsFpuRegister() ? source.fpu_reg()
1646 : destination.fpu_reg(); 1667 : destination.fpu_reg();
1647 const Address& slot_address = source.IsFpuRegister() 1668 const Address& slot_address = source.IsFpuRegister()
1648 ? destination.ToStackSlotAddress() 1669 ? destination.ToStackSlotAddress()
1649 : source.ToStackSlotAddress(); 1670 : source.ToStackSlotAddress();
1650 1671
1651 __ movsd(XMM0, slot_address); 1672 if (double_width) {
1652 __ movsd(slot_address, reg); 1673 __ movsd(XMM0, slot_address);
1674 __ movsd(slot_address, reg);
1675 } else {
1676 __ movups(XMM0, slot_address);
1677 __ movups(slot_address, reg);
1678 }
1653 __ movaps(reg, XMM0); 1679 __ movaps(reg, XMM0);
1654 } else { 1680 } else {
1655 UNREACHABLE(); 1681 UNREACHABLE();
1656 } 1682 }
1657 1683
1658 // The swap of source and destination has executed a move from source to 1684 // The swap of source and destination has executed a move from source to
1659 // destination. 1685 // destination.
1660 move->Eliminate(); 1686 move->Eliminate();
1661 1687
1662 // Any unperformed (including pending) move with a source of either 1688 // Any unperformed (including pending) move with a source of either
(...skipping 55 matching lines...) Expand 10 before | Expand all | Expand 10 after
1718 __ popl(ECX); 1744 __ popl(ECX);
1719 __ popl(EAX); 1745 __ popl(EAX);
1720 } 1746 }
1721 1747
1722 1748
1723 #undef __ 1749 #undef __
1724 1750
1725 } // namespace dart 1751 } // namespace dart
1726 1752
1727 #endif // defined TARGET_ARCH_IA32 1753 #endif // defined TARGET_ARCH_IA32
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