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1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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389 llvm::SmallVectorImpl<int32_t> &Permutation, | 389 llvm::SmallVectorImpl<int32_t> &Permutation, |
390 const llvm::SmallBitVector &ExcludeRegisters, | 390 const llvm::SmallBitVector &ExcludeRegisters, |
391 uint64_t Salt) { | 391 uint64_t Salt) { |
392 // TODO(stichnot): Declaring Permutation this way loses type/size | 392 // TODO(stichnot): Declaring Permutation this way loses type/size |
393 // information. Fix this in conjunction with the caller-side TODO. | 393 // information. Fix this in conjunction with the caller-side TODO. |
394 assert(Permutation.size() >= RegisterSet::Reg_NUM); | 394 assert(Permutation.size() >= RegisterSet::Reg_NUM); |
395 // Expected upper bound on the number of registers in a single equivalence | 395 // Expected upper bound on the number of registers in a single equivalence |
396 // class. For x86-32, this would comprise the 8 XMM registers. This is for | 396 // class. For x86-32, this would comprise the 8 XMM registers. This is for |
397 // performance, not correctness. | 397 // performance, not correctness. |
398 static const unsigned MaxEquivalenceClassSize = 8; | 398 static const unsigned MaxEquivalenceClassSize = 8; |
399 typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList; | 399 using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>; |
400 typedef std::map<uint32_t, RegisterList> EquivalenceClassMap; | 400 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
401 EquivalenceClassMap EquivalenceClasses; | 401 EquivalenceClassMap EquivalenceClasses; |
402 SizeT NumShuffled = 0, NumPreserved = 0; | 402 SizeT NumShuffled = 0, NumPreserved = 0; |
403 | 403 |
404 // Build up the equivalence classes of registers by looking at the register | 404 // Build up the equivalence classes of registers by looking at the register |
405 // properties as well as whether the registers should be explicitly excluded | 405 // properties as well as whether the registers should be explicitly excluded |
406 // from shuffling. | 406 // from shuffling. |
407 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 407 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
408 frameptr, isI8, isInt, isFP) \ | 408 frameptr, isI8, isInt, isFP) \ |
409 if (ExcludeRegisters[RegisterSet::val]) { \ | 409 if (ExcludeRegisters[RegisterSet::val]) { \ |
410 /* val stays the same in the resulting permutation. */ \ | 410 /* val stays the same in the resulting permutation. */ \ |
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741 | 741 |
742 } // end of namespace X86Internal | 742 } // end of namespace X86Internal |
743 | 743 |
744 namespace X8632 { | 744 namespace X8632 { |
745 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>; | 745 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>; |
746 } // end of namespace X8632 | 746 } // end of namespace X8632 |
747 | 747 |
748 } // end of namespace Ice | 748 } // end of namespace Ice |
749 | 749 |
750 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 750 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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