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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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145 RandomNumberGenerator &RNG) override; | 145 RandomNumberGenerator &RNG) override; |
146 | 146 |
147 enum OperandLegalization { | 147 enum OperandLegalization { |
148 Legal_None = 0, | 148 Legal_None = 0, |
149 Legal_Reg = 1 << 0, /// physical register, not stack location | 149 Legal_Reg = 1 << 0, /// physical register, not stack location |
150 Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated | 150 Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated |
151 /// small immediates, or shifted registers. | 151 /// small immediates, or shifted registers. |
152 Legal_Mem = 1 << 2, /// includes [r0, r1 lsl #2] as well as [sp, #12] | 152 Legal_Mem = 1 << 2, /// includes [r0, r1 lsl #2] as well as [sp, #12] |
153 Legal_All = ~Legal_None | 153 Legal_All = ~Legal_None |
154 }; | 154 }; |
155 typedef uint32_t LegalMask; | 155 using LegalMask = uint32_t; |
156 Operand *legalize(Operand *From, LegalMask Allowed = Legal_All, | 156 Operand *legalize(Operand *From, LegalMask Allowed = Legal_All, |
157 int32_t RegNum = Variable::NoRegister); | 157 int32_t RegNum = Variable::NoRegister); |
158 Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister); | 158 Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister); |
159 OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty); | 159 OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty); |
160 | 160 |
161 Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); | 161 Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); |
162 static Type stackSlotType(); | 162 static Type stackSlotType(); |
163 Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister); | 163 Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister); |
164 void alignRegisterPow2(Variable *Reg, uint32_t Align); | 164 void alignRegisterPow2(Variable *Reg, uint32_t Align); |
165 | 165 |
166 /// Returns a vector in a register with the given constant entries. | 166 /// Returns a vector in a register with the given constant entries. |
167 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister); | 167 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister); |
168 | 168 |
169 void | 169 void |
170 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 170 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
171 const llvm::SmallBitVector &ExcludeRegisters, | 171 const llvm::SmallBitVector &ExcludeRegisters, |
172 uint64_t Salt) const override; | 172 uint64_t Salt) const override; |
173 | 173 |
174 // If a divide-by-zero check is needed, inserts a: | 174 // If a divide-by-zero check is needed, inserts a: |
175 // test; branch .LSKIP; trap; .LSKIP: <continuation>. | 175 // test; branch .LSKIP; trap; .LSKIP: <continuation>. |
176 // If no check is needed nothing is inserted. | 176 // If no check is needed nothing is inserted. |
177 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi); | 177 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi); |
178 typedef void (TargetARM32::*ExtInstr)(Variable *, Variable *, | 178 using ExtInstr = void (TargetARM32::*)(Variable *, Variable *, |
179 CondARM32::Cond); | 179 CondARM32::Cond); |
180 typedef void (TargetARM32::*DivInstr)(Variable *, Variable *, Variable *, | 180 using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *, |
181 CondARM32::Cond); | 181 CondARM32::Cond); |
182 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1, | 182 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1, |
183 ExtInstr ExtFunc, DivInstr DivFunc, | 183 ExtInstr ExtFunc, DivInstr DivFunc, |
184 const char *DivHelperName, bool IsRemainder); | 184 const char *DivHelperName, bool IsRemainder); |
185 | 185 |
186 void lowerCLZ(Variable *Dest, Variable *ValLo, Variable *ValHi); | 186 void lowerCLZ(Variable *Dest, Variable *ValLo, Variable *ValHi); |
187 | 187 |
188 // The following are helpers that insert lowered ARM32 instructions | 188 // The following are helpers that insert lowered ARM32 instructions |
189 // with minimal syntactic overhead, so that the lowering code can | 189 // with minimal syntactic overhead, so that the lowering code can |
190 // look as close to assembly as practical. | 190 // look as close to assembly as practical. |
191 | 191 |
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523 | 523 |
524 private: | 524 private: |
525 ~TargetHeaderARM32() = default; | 525 ~TargetHeaderARM32() = default; |
526 | 526 |
527 TargetARM32Features CPUFeatures; | 527 TargetARM32Features CPUFeatures; |
528 }; | 528 }; |
529 | 529 |
530 } // end of namespace Ice | 530 } // end of namespace Ice |
531 | 531 |
532 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 532 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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