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| 1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// | 1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 32 explicit LinearScan(Cfg *Func); | 32 explicit LinearScan(Cfg *Func); |
| 33 void init(RegAllocKind Kind); | 33 void init(RegAllocKind Kind); |
| 34 void scan(const llvm::SmallBitVector &RegMask, bool Randomized); | 34 void scan(const llvm::SmallBitVector &RegMask, bool Randomized); |
| 35 void dump(Cfg *Func) const; | 35 void dump(Cfg *Func) const; |
| 36 | 36 |
| 37 // TODO(stichnot): Statically choose the size based on the target being | 37 // TODO(stichnot): Statically choose the size based on the target being |
| 38 // compiled. | 38 // compiled. |
| 39 static constexpr size_t REGS_SIZE = 32; | 39 static constexpr size_t REGS_SIZE = 32; |
| 40 | 40 |
| 41 private: | 41 private: |
| 42 typedef std::vector<Variable *> OrderedRanges; | 42 using OrderedRanges = std::vector<Variable *>; |
| 43 typedef std::vector<Variable *> UnorderedRanges; | 43 using UnorderedRanges = std::vector<Variable *>; |
| 44 | 44 |
| 45 class IterationState { | 45 class IterationState { |
| 46 IterationState(const IterationState &) = delete; | 46 IterationState(const IterationState &) = delete; |
| 47 IterationState operator=(const IterationState &) = delete; | 47 IterationState operator=(const IterationState &) = delete; |
| 48 | 48 |
| 49 public: | 49 public: |
| 50 IterationState() = default; | 50 IterationState() = default; |
| 51 Variable *Cur = nullptr; | 51 Variable *Cur = nullptr; |
| 52 Variable *Prefer = nullptr; | 52 Variable *Prefer = nullptr; |
| 53 int32_t PreferReg = Variable::NoRegister; | 53 int32_t PreferReg = Variable::NoRegister; |
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| 114 llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases; | 114 llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases; |
| 115 bool FindPreference = false; | 115 bool FindPreference = false; |
| 116 bool FindOverlap = false; | 116 bool FindOverlap = false; |
| 117 | 117 |
| 118 const bool Verbose; | 118 const bool Verbose; |
| 119 }; | 119 }; |
| 120 | 120 |
| 121 } // end of namespace Ice | 121 } // end of namespace Ice |
| 122 | 122 |
| 123 #endif // SUBZERO_SRC_ICEREGALLOC_H | 123 #endif // SUBZERO_SRC_ICEREGALLOC_H |
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