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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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408 // Vmov can also be used to insert-element. E.g., | 408 // Vmov can also be used to insert-element. E.g., |
409 // "vmov.8 d0[1], r0" | 409 // "vmov.8 d0[1], r0" |
410 // but insert-element is a "two-address" operation where only part of the | 410 // but insert-element is a "two-address" operation where only part of the |
411 // register is modified. This cannot model that. | 411 // register is modified. This cannot model that. |
412 // | 412 // |
413 // This represents the simple single source, single dest variants only. | 413 // This represents the simple single source, single dest variants only. |
414 void _vmov(Variable *Dest, Operand *Src0) { | 414 void _vmov(Variable *Dest, Operand *Src0) { |
415 constexpr CondARM32::Cond Pred = CondARM32::AL; | 415 constexpr CondARM32::Cond Pred = CondARM32::AL; |
416 Context.insert(InstARM32Vmov::create(Func, Dest, Src0, Pred)); | 416 Context.insert(InstARM32Vmov::create(Func, Dest, Src0, Pred)); |
417 } | 417 } |
| 418 // This represents the single source, multi dest variant. |
| 419 void _vmov(InstARM32Vmov::RegisterPair Dests, Variable *Src0) { |
| 420 constexpr CondARM32::Cond Pred = CondARM32::AL; |
| 421 Context.insert(InstARM32Vmov::create(Func, Dests, Src0, Pred)); |
| 422 // The Vmov instruction created above does not define Dests._1. Therefore |
| 423 // we add a Dest._1 = FakeDef pseudo instruction. |
| 424 Context.insert(InstFakeDef::create(Func, Dests._1)); |
| 425 } |
| 426 // This represents the multi source, single dest variant. |
| 427 void _vmov(Variable *Dest, InstARM32Vmov::RegisterPair Srcs) { |
| 428 constexpr CondARM32::Cond Pred = CondARM32::AL; |
| 429 Context.insert(InstARM32Vmov::create(Func, Dest, Srcs, Pred)); |
| 430 } |
418 void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) { | 431 void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) { |
419 Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1)); | 432 Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1)); |
420 } | 433 } |
421 void _vsqrt(Variable *Dest, Variable *Src, | 434 void _vsqrt(Variable *Dest, Variable *Src, |
422 CondARM32::Cond Pred = CondARM32::AL) { | 435 CondARM32::Cond Pred = CondARM32::AL) { |
423 Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred)); | 436 Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred)); |
424 } | 437 } |
425 void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) { | 438 void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) { |
426 Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1)); | 439 Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1)); |
427 } | 440 } |
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523 | 536 |
524 private: | 537 private: |
525 ~TargetHeaderARM32() = default; | 538 ~TargetHeaderARM32() = default; |
526 | 539 |
527 TargetARM32Features CPUFeatures; | 540 TargetARM32Features CPUFeatures; |
528 }; | 541 }; |
529 | 542 |
530 } // end of namespace Ice | 543 } // end of namespace Ice |
531 | 544 |
532 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 545 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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