Subzero. Implements the scalar bitcast operations for ARM32.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2090 matching lines @@
     //     t2.i32 = vmov t1.fp
     //     dest.int = conv t2.i32     @ Truncates the result if needed.
     // fptoui:
     //     t1.fp = vcvt src0.fp
     //     t2.u32 = vmov t1.fp
     //     dest.uint = conv t2.u32    @ Truncates the result if needed.
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
       break;
     } else if (Dest->getType() == IceType_i64) {
+      split64(Dest);
+      Context.insert(InstFakeDef::create(Func, Dest->getLo()));
+      Context.insert(InstFakeDef::create(Func, Dest->getHi()));
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
     const bool DestIsSigned = CastKind == InstCast::Fptosi;
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T_fp = makeReg(IceType_f32);
     if (isFloat32Asserting32Or64(Src0->getType())) {
       _vcvt(T_fp, Src0R,
             DestIsSigned ? InstARM32Vcvt::S2si : InstARM32Vcvt::S2ui);
     } else {
@@ skipping 16 matching lines @@
     //     t1.i32 = sext src.int    @ sign-extends src0 if needed.
     //     t2.fp32 = vmov t1.i32
     //     t3.fp = vcvt.{fp}.s32    @ fp is either f32 or f64
     // uitofp:
     //     t1.i32 = zext src.int    @ zero-extends src0 if needed.
     //     t2.fp32 = vmov t1.i32
     //     t3.fp = vcvt.{fp}.s32    @ fp is either f32 or f64
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
       break;
-    } else if (Src0->getType() == IceType_i64) {
+    }
+    if (Src0->getType() == IceType_i64) {
+      // avoid cryptic liveness errors
+      Context.insert(InstFakeDef::create(Func, Dest));
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
     const bool SourceIsSigned = CastKind == InstCast::Sitofp;
     if (Src0->getType() != IceType_i32) {
       Variable *Src0R_32 = makeReg(IceType_i32);
       lowerCast(InstCast::create(Func, SourceIsSigned ? InstCast::Sext
                                                       : InstCast::Zext,
                                  Src0R_32, Src0));
       Src0 = Src0R_32;
@@ skipping 13 matching lines @@
     _mov(Dest, T);
     break;
   }
   case InstCast::Bitcast: {
     Operand *Src0 = Inst->getSrc(0);
     if (Dest->getType() == Src0->getType()) {
       InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
-    UnimplementedError(Func->getContext()->getFlags());
+    Type DestType = Dest->getType();
+    switch (DestType) {
+    case IceType_NUM:
+    case IceType_void:
+      llvm::report_fatal_error("Unexpected bitcast.");
+    case IceType_i1:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v4i1:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_i8:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_i16:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_i32:
+    case IceType_f32: {
+      Variable *Src0R = legalizeToReg(Src0);
+      Variable *T = makeReg(DestType);
+      _vmov(T, Src0R);
+      lowerAssign(InstAssign::create(Func, Dest, T));
+      break;
+    }
+    case IceType_i64: {
+      // t0, t1 <- src0
+      // dest[31..0]  = t0
+      // dest[63..32] = t1
+      assert(Src0->getType() == IceType_f64);
+      Variable *T0 = makeReg(IceType_i32);
+      Variable *T1 = makeReg(IceType_i32);
+      Variable *Src0R = legalizeToReg(Src0);
+      split64(Dest);
+      _vmov(InstARM32Vmov::RegisterPair(T0, T1), Src0R);
+      lowerAssign(InstAssign::create(Func, Dest->getLo(), T0));
+      lowerAssign(InstAssign::create(Func, Dest->getHi(), T1));
+      break;
+    }
+    case IceType_f64: {
+      // T0 <- lo(src)
+      // T1 <- hi(src)
+      // vmov T2, T0, T1
+      // Dest <- T2
+      assert(Src0->getType() == IceType_i64);
+      Variable *SrcLo = legalizeToReg(loOperand(Src0));
+      Variable *SrcHi = legalizeToReg(hiOperand(Src0));
+      Variable *T = makeReg(IceType_f64);
+      _vmov(T, InstARM32Vmov::RegisterPair(SrcLo, SrcHi));
+      lowerAssign(InstAssign::create(Func, Dest, T));
+      break;
+    }
+    case IceType_v8i1:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v16i1:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v8i16:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v16i8:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v4i32:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    case IceType_v4f32:
+      UnimplementedError(Func->getContext()->getFlags());
+      break;
+    }
     break;
   }
   }
 }
 
 void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
   (void)Inst;
   UnimplementedError(Func->getContext()->getFlags());
 }
 
@@ skipping 937 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice