Subzero. Implements the scalar bitcast operations for ARM32.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 385 matching lines @@
 template <> const char *InstARM32Rev::Opcode = "rev";
 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h
 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h
 // FP
 template <> const char *InstARM32Vsqrt::Opcode = "vsqrt";
 // Mov-like ops
 template <> const char *InstARM32Ldr::Opcode = "ldr";
 template <> const char *InstARM32Mov::Opcode = "mov";
 // FP
 template <> const char *InstARM32Vldr::Opcode = "vldr";
-template <> const char *InstARM32Vmov::Opcode = "vmov";
 // Three-addr ops
 template <> const char *InstARM32Adc::Opcode = "adc";
 template <> const char *InstARM32Add::Opcode = "add";
 template <> const char *InstARM32And::Opcode = "and";
 template <> const char *InstARM32Asr::Opcode = "asr";
 template <> const char *InstARM32Bic::Opcode = "bic";
 template <> const char *InstARM32Eor::Opcode = "eor";
 template <> const char *InstARM32Lsl::Opcode = "lsl";
 template <> const char *InstARM32Lsr::Opcode = "lsr";
 template <> const char *InstARM32Mul::Opcode = "mul";
@@ skipping 74 matching lines @@
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 template <> void InstARM32Vldr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
-template <> void InstARM32Vmov::emit(const Cfg *Func) const {
+void InstARM32Vmov::emitMultiDestSingleSource(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  assert(CondARM32::AL == getPredicate());
   Ostream &Str = Func->getContext()->getStrEmit();
-  assert(getSrcSize() == 1);
+  Variable *Dest0 = getDest();
+  Operand *Src0 = getSrc(0);
+
+  assert(Dest0->hasReg());
+  assert(Dest1->hasReg());
+  assert(!llvm::isa<OperandARM32Mem>(Src0));
+
+  Str << "\t"
+      << "vmov"
+      << "\t";
+  Dest0->emit(Func);
+  Str << ", ";
+  Dest1->emit(Func);
+  Str << ", ";
+  Src0->emit(Func);
+}
+
+void InstARM32Vmov::emitSingleDestMultiSource(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Variable *Dest0 = getDest();
+  Operand *Src0 = getSrc(0);
+  Operand *Src1 = getSrc(1);
+
+  assert(Dest0->hasReg());
+  assert(!llvm::isa<OperandARM32Mem>(Src0));
+  assert(!llvm::isa<OperandARM32Mem>(Src1));
+
+  Str << "\t"
+      << "vmov"
+      << "\t";
+  Dest0->emit(Func);
+  Str << ", ";
+  Src0->emit(Func);
+  Str << ", ";
+  Src1->emit(Func);
+}
+
+void InstARM32Vmov::emitSingleDestSingleSource(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
   if (Dest->hasReg()) {
-    IceString ActualOpcode = Opcode;
+    IceString ActualOpcode = "vmov";
     Operand *Src0 = getSrc(0);
     if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) {
       if (!Src0V->hasReg()) {
         ActualOpcode = IceString("vldr");
       }
     } else {
       if (llvm::isa<OperandARM32Mem>(Src0))
         ActualOpcode = IceString("vldr");
     }
     Str << "\t" << ActualOpcode << "\t";
     getDest()->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
     Str << "\t"
            "vstr"
            "\t";
     Src0->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   }
 }
 
-template <> void InstARM32Vmov::emitIAS(const Cfg *Func) const {
+void InstARM32Vmov::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(CondARM32::AL == getPredicate());
+  assert(isMultiDest() + isMultiSource() <= 1 && "Invalid vmov type.");
+  if (isMultiDest()) {
+    emitMultiDestSingleSource(Func);
+    return;
+  }
+
+  if (isMultiSource()) {
+    emitSingleDestMultiSource(Func);
+    return;
+  }
+
+  emitSingleDestSingleSource(Func);
+}
+
+void InstARM32Vmov::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
+void InstARM32Vmov::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  dumpOpcodePred(Str, "vmov", getDest()->getType());
+  Str << " ";
+  dumpDest(Func);
+  Str << ", ";
+  dumpSources(Func);
+}
+
 void InstARM32Br::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
       << "b" << getPredicate() << "\t";
   if (Label) {
     Str << Label->getName(Func);
   } else {
     if (isUnconditionalBranch()) {
@@ skipping 531 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice