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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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396 template <> const char *InstARM32Rev::Opcode = "rev"; | 396 template <> const char *InstARM32Rev::Opcode = "rev"; |
397 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h | 397 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h |
398 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h | 398 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h |
399 // FP | 399 // FP |
400 template <> const char *InstARM32Vsqrt::Opcode = "vsqrt"; | 400 template <> const char *InstARM32Vsqrt::Opcode = "vsqrt"; |
401 // Mov-like ops | 401 // Mov-like ops |
402 template <> const char *InstARM32Ldr::Opcode = "ldr"; | 402 template <> const char *InstARM32Ldr::Opcode = "ldr"; |
403 template <> const char *InstARM32Mov::Opcode = "mov"; | 403 template <> const char *InstARM32Mov::Opcode = "mov"; |
404 // FP | 404 // FP |
405 template <> const char *InstARM32Vldr::Opcode = "vldr"; | 405 template <> const char *InstARM32Vldr::Opcode = "vldr"; |
406 template <> const char *InstARM32Vmov::Opcode = "vmov"; | |
407 // Three-addr ops | 406 // Three-addr ops |
408 template <> const char *InstARM32Adc::Opcode = "adc"; | 407 template <> const char *InstARM32Adc::Opcode = "adc"; |
409 template <> const char *InstARM32Add::Opcode = "add"; | 408 template <> const char *InstARM32Add::Opcode = "add"; |
410 template <> const char *InstARM32And::Opcode = "and"; | 409 template <> const char *InstARM32And::Opcode = "and"; |
411 template <> const char *InstARM32Asr::Opcode = "asr"; | 410 template <> const char *InstARM32Asr::Opcode = "asr"; |
412 template <> const char *InstARM32Bic::Opcode = "bic"; | 411 template <> const char *InstARM32Bic::Opcode = "bic"; |
413 template <> const char *InstARM32Eor::Opcode = "eor"; | 412 template <> const char *InstARM32Eor::Opcode = "eor"; |
414 template <> const char *InstARM32Lsl::Opcode = "lsl"; | 413 template <> const char *InstARM32Lsl::Opcode = "lsl"; |
415 template <> const char *InstARM32Lsr::Opcode = "lsr"; | 414 template <> const char *InstARM32Lsr::Opcode = "lsr"; |
416 template <> const char *InstARM32Mul::Opcode = "mul"; | 415 template <> const char *InstARM32Mul::Opcode = "mul"; |
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491 Str << ", "; | 490 Str << ", "; |
492 getSrc(0)->emit(Func); | 491 getSrc(0)->emit(Func); |
493 } | 492 } |
494 | 493 |
495 template <> void InstARM32Vldr::emitIAS(const Cfg *Func) const { | 494 template <> void InstARM32Vldr::emitIAS(const Cfg *Func) const { |
496 assert(getSrcSize() == 1); | 495 assert(getSrcSize() == 1); |
497 (void)Func; | 496 (void)Func; |
498 llvm_unreachable("Not yet implemented"); | 497 llvm_unreachable("Not yet implemented"); |
499 } | 498 } |
500 | 499 |
501 template <> void InstARM32Vmov::emit(const Cfg *Func) const { | 500 void InstARM32Vmov::emitMultiDestSingleSource(const Cfg *Func) const { |
502 if (!BuildDefs::dump()) | 501 if (!BuildDefs::dump()) |
503 return; | 502 return; |
504 assert(CondARM32::AL == getPredicate()); | |
505 Ostream &Str = Func->getContext()->getStrEmit(); | 503 Ostream &Str = Func->getContext()->getStrEmit(); |
506 assert(getSrcSize() == 1); | 504 Variable *Dest0 = getDest(); |
| 505 Operand *Src0 = getSrc(0); |
| 506 |
| 507 assert(Dest0->hasReg()); |
| 508 assert(Dest1->hasReg()); |
| 509 assert(!llvm::isa<OperandARM32Mem>(Src0)); |
| 510 |
| 511 Str << "\t" |
| 512 << "vmov" |
| 513 << "\t"; |
| 514 Dest0->emit(Func); |
| 515 Str << ", "; |
| 516 Dest1->emit(Func); |
| 517 Str << ", "; |
| 518 Src0->emit(Func); |
| 519 } |
| 520 |
| 521 void InstARM32Vmov::emitSingleDestMultiSource(const Cfg *Func) const { |
| 522 if (!BuildDefs::dump()) |
| 523 return; |
| 524 Ostream &Str = Func->getContext()->getStrEmit(); |
| 525 Variable *Dest0 = getDest(); |
| 526 Operand *Src0 = getSrc(0); |
| 527 Operand *Src1 = getSrc(1); |
| 528 |
| 529 assert(Dest0->hasReg()); |
| 530 assert(!llvm::isa<OperandARM32Mem>(Src0)); |
| 531 assert(!llvm::isa<OperandARM32Mem>(Src1)); |
| 532 |
| 533 Str << "\t" |
| 534 << "vmov" |
| 535 << "\t"; |
| 536 Dest0->emit(Func); |
| 537 Str << ", "; |
| 538 Src0->emit(Func); |
| 539 Str << ", "; |
| 540 Src1->emit(Func); |
| 541 } |
| 542 |
| 543 void InstARM32Vmov::emitSingleDestSingleSource(const Cfg *Func) const { |
| 544 if (!BuildDefs::dump()) |
| 545 return; |
| 546 Ostream &Str = Func->getContext()->getStrEmit(); |
507 Variable *Dest = getDest(); | 547 Variable *Dest = getDest(); |
508 if (Dest->hasReg()) { | 548 if (Dest->hasReg()) { |
509 IceString ActualOpcode = Opcode; | 549 IceString ActualOpcode = "vmov"; |
510 Operand *Src0 = getSrc(0); | 550 Operand *Src0 = getSrc(0); |
511 if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) { | 551 if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) { |
512 if (!Src0V->hasReg()) { | 552 if (!Src0V->hasReg()) { |
513 ActualOpcode = IceString("vldr"); | 553 ActualOpcode = IceString("vldr"); |
514 } | 554 } |
515 } else { | 555 } else { |
516 if (llvm::isa<OperandARM32Mem>(Src0)) | 556 if (llvm::isa<OperandARM32Mem>(Src0)) |
517 ActualOpcode = IceString("vldr"); | 557 ActualOpcode = IceString("vldr"); |
518 } | 558 } |
519 Str << "\t" << ActualOpcode << "\t"; | 559 Str << "\t" << ActualOpcode << "\t"; |
520 getDest()->emit(Func); | 560 getDest()->emit(Func); |
521 Str << ", "; | 561 Str << ", "; |
522 getSrc(0)->emit(Func); | 562 getSrc(0)->emit(Func); |
523 } else { | 563 } else { |
524 Variable *Src0 = llvm::cast<Variable>(getSrc(0)); | 564 Variable *Src0 = llvm::cast<Variable>(getSrc(0)); |
525 assert(Src0->hasReg()); | 565 assert(Src0->hasReg()); |
526 Str << "\t" | 566 Str << "\t" |
527 "vstr" | 567 "vstr" |
528 "\t"; | 568 "\t"; |
529 Src0->emit(Func); | 569 Src0->emit(Func); |
530 Str << ", "; | 570 Str << ", "; |
531 Dest->emit(Func); | 571 Dest->emit(Func); |
532 } | 572 } |
533 } | 573 } |
534 | 574 |
535 template <> void InstARM32Vmov::emitIAS(const Cfg *Func) const { | 575 void InstARM32Vmov::emit(const Cfg *Func) const { |
| 576 if (!BuildDefs::dump()) |
| 577 return; |
| 578 assert(CondARM32::AL == getPredicate()); |
| 579 assert(isMultiDest() + isMultiSource() <= 1 && "Invalid vmov type."); |
| 580 if (isMultiDest()) { |
| 581 emitMultiDestSingleSource(Func); |
| 582 return; |
| 583 } |
| 584 |
| 585 if (isMultiSource()) { |
| 586 emitSingleDestMultiSource(Func); |
| 587 return; |
| 588 } |
| 589 |
| 590 emitSingleDestSingleSource(Func); |
| 591 } |
| 592 |
| 593 void InstARM32Vmov::emitIAS(const Cfg *Func) const { |
536 assert(getSrcSize() == 1); | 594 assert(getSrcSize() == 1); |
537 (void)Func; | 595 (void)Func; |
538 llvm_unreachable("Not yet implemented"); | 596 llvm_unreachable("Not yet implemented"); |
539 } | 597 } |
540 | 598 |
| 599 void InstARM32Vmov::dump(const Cfg *Func) const { |
| 600 if (!BuildDefs::dump()) |
| 601 return; |
| 602 Ostream &Str = Func->getContext()->getStrDump(); |
| 603 dumpOpcodePred(Str, "vmov", getDest()->getType()); |
| 604 Str << " "; |
| 605 dumpDest(Func); |
| 606 Str << ", "; |
| 607 dumpSources(Func); |
| 608 } |
| 609 |
541 void InstARM32Br::emit(const Cfg *Func) const { | 610 void InstARM32Br::emit(const Cfg *Func) const { |
542 if (!BuildDefs::dump()) | 611 if (!BuildDefs::dump()) |
543 return; | 612 return; |
544 Ostream &Str = Func->getContext()->getStrEmit(); | 613 Ostream &Str = Func->getContext()->getStrEmit(); |
545 Str << "\t" | 614 Str << "\t" |
546 << "b" << getPredicate() << "\t"; | 615 << "b" << getPredicate() << "\t"; |
547 if (Label) { | 616 if (Label) { |
548 Str << Label->getName(Func); | 617 Str << Label->getName(Func); |
549 } else { | 618 } else { |
550 if (isUnconditionalBranch()) { | 619 if (isUnconditionalBranch()) { |
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1082 if (getShiftOp() != kNoShift) { | 1151 if (getShiftOp() != kNoShift) { |
1083 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; | 1152 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; |
1084 if (Func) | 1153 if (Func) |
1085 getShiftAmt()->dump(Func); | 1154 getShiftAmt()->dump(Func); |
1086 else | 1155 else |
1087 getShiftAmt()->dump(Str); | 1156 getShiftAmt()->dump(Str); |
1088 } | 1157 } |
1089 } | 1158 } |
1090 | 1159 |
1091 } // end of namespace Ice | 1160 } // end of namespace Ice |
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