Revert "VM: New calling convention for generated code."

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 286 matching lines @@
       continue;
     }
 
     // 6. Otherwise, the value can't be encoded.
     return false;
   }
 }
 
 
 void Assembler::LoadPoolPointer(Register pp) {
-  CheckCodePointer();
-  ldr(pp, FieldAddress(CODE_REG, Code::object_pool_offset()));
+  const intptr_t object_pool_pc_dist =
+    Instructions::HeaderSize() - Instructions::object_pool_offset() +
+    CodeSize();
+  // PP <- Read(PC - object_pool_pc_dist).
+  ldr(pp, Address::PC(-object_pool_pc_dist));
 
   // When in the PP register, the pool pointer is untagged. When we
   // push it on the stack with TagAndPushPP it is tagged again. PopAndUntagPP
   // then untags when restoring from the stack. This will make loading from the
   // object pool only one instruction for the first 4096 entries. Otherwise,
   // because the offset wouldn't be aligned, it would be only one instruction
   // for the first 64 entries.
   sub(pp, pp, Operand(kHeapObjectTag));
   set_constant_pool_allowed(pp == PP);
 }
 
 
-void Assembler::LoadWordFromPoolOffset(Register dst,
-                                       uint32_t offset,
-                                       Register pp) {
-  ASSERT((pp != PP) || constant_pool_allowed());
-  ASSERT(dst != pp);
+void Assembler::LoadWordFromPoolOffset(Register dst, uint32_t offset) {
+  ASSERT(constant_pool_allowed());
+  ASSERT(dst != PP);
   Operand op;
   const uint32_t upper20 = offset & 0xfffff000;
   if (Address::CanHoldOffset(offset)) {
-    ldr(dst, Address(pp, offset));
+    ldr(dst, Address(PP, offset));
   } else if (Operand::CanHold(upper20, kXRegSizeInBits, &op) ==
              Operand::Immediate) {
     const uint32_t lower12 = offset & 0x00000fff;
     ASSERT(Address::CanHoldOffset(lower12));
-    add(dst, pp, op);
+    add(dst, PP, op);
     ldr(dst, Address(dst, lower12));
   } else {
     const uint16_t offset_low = Utils::Low16Bits(offset);
     const uint16_t offset_high = Utils::High16Bits(offset);
     movz(dst, Immediate(offset_low), 0);
     if (offset_high != 0) {
       movk(dst, Immediate(offset_high), 1);
     }
-    ldr(dst, Address(pp, dst));
+    ldr(dst, Address(PP, dst));
   }
 }
 
 
 void Assembler::LoadWordFromPoolOffsetFixed(Register dst, uint32_t offset) {
   ASSERT(constant_pool_allowed());
   ASSERT(dst != PP);
   Operand op;
   const uint32_t upper20 = offset & 0xfffff000;
   const uint32_t lower12 = offset & 0x00000fff;
@@ skipping 233 matching lines @@
 
 void Assembler::LoadDImmediate(VRegister vd, double immd) {
   if (!fmovdi(vd, immd)) {
     int64_t imm = bit_cast<int64_t, double>(immd);
     LoadImmediate(TMP, imm);
     fmovdr(vd, TMP);
   }
 }
 
 
-void Assembler::Branch(const StubEntry& stub_entry,
-                       Register pp,
-                       Patchability patchable) {
-  const Code& target = Code::Handle(stub_entry.code());
-  const int32_t offset = ObjectPool::element_offset(
-      object_pool_wrapper_.FindObject(target, patchable));
-  LoadWordFromPoolOffset(CODE_REG, offset, pp);
-  ldr(TMP, FieldAddress(CODE_REG, Code::entry_point_offset()));
+void Assembler::Branch(const ExternalLabel* label) {
+  LoadExternalLabel(TMP, label);
+  br(TMP);
+}
+
+
+void Assembler::Branch(const StubEntry& stub_entry) {
+  const ExternalLabel label(stub_entry.EntryPoint());
+  Branch(&label);
+}
+
+
+void Assembler::BranchPatchable(const ExternalLabel* label) {
+  // TODO(zra): Use LoadExternalLabelFixed if possible.
+  LoadImmediateFixed(TMP, label->address());
   br(TMP);
 }
 
 void Assembler::BranchPatchable(const StubEntry& stub_entry) {
-  Branch(stub_entry, PP, kPatchable);
+  BranchPatchable(&stub_entry.label());
 }
 
 
-void Assembler::BranchLink(const StubEntry& stub_entry,
-                           Patchability patchable) {
-  const Code& target = Code::Handle(stub_entry.code());
-  const int32_t offset = ObjectPool::element_offset(
-      object_pool_wrapper_.FindObject(target, patchable));
-  LoadWordFromPoolOffset(CODE_REG, offset);
-  ldr(TMP, FieldAddress(CODE_REG, Code::entry_point_offset()));
+void Assembler::BranchLink(const ExternalLabel* label) {
+  LoadExternalLabel(TMP, label);
+  blr(TMP);
+}
+
+
+void Assembler::BranchLink(const StubEntry& stub_entry) {
+  BranchLink(&stub_entry.label());
+}
+
+
+void Assembler::BranchLinkPatchable(const ExternalLabel* label) {
+  LoadExternalLabelFixed(TMP, label, kPatchable);
   blr(TMP);
 }
 
 
 void Assembler::BranchLinkPatchable(const StubEntry& stub_entry) {
-  BranchLink(stub_entry, kPatchable);
+  BranchLinkPatchable(&stub_entry.label());
 }
 
 
 void Assembler::AddImmediate(Register dest, Register rn, int64_t imm) {
   Operand op;
   if (imm == 0) {
     if (dest != rn) {
       mov(dest, rn);
     }
     return;
@@ skipping 269 matching lines @@
   }
   // A store buffer update is required.
   if (value != R0) {
     // Preserve R0.
     Push(R0);
   }
   Push(LR);
   if (object != R0) {
     mov(R0, object);
   }
-  ldr(CODE_REG, Address(THR, Thread::update_store_buffer_code_offset()));
   ldr(TMP, Address(THR, Thread::update_store_buffer_entry_point_offset()));
   blr(TMP);
   Pop(LR);
   if (value != R0) {
     // Restore R0.
     Pop(R0);
   }
   Bind(&done);
 }
 
@@ skipping 156 matching lines @@
   // the C++ world.
   if (frame_space != 0) {
     AddImmediate(SP, SP, -frame_space);
   }
   if (OS::ActivationFrameAlignment() > 1) {
     andi(SP, SP, Immediate(~(OS::ActivationFrameAlignment() - 1)));
   }
 }
 
 
-void Assembler::RestoreCodePointer() {
-  ldr(CODE_REG, Address(FP, kPcMarkerSlotFromFp * kWordSize));
-  CheckCodePointer();
-}
-
-
-void Assembler::CheckCodePointer() {
-#ifdef DEBUG
-  Label cid_ok, instructions_ok;
-  Push(R0);
-  CompareClassId(CODE_REG, kCodeCid);
-  b(&cid_ok, EQ);
-  brk(0);
-  Bind(&cid_ok);
-
-  const intptr_t entry_offset =
-      CodeSize() + Instructions::HeaderSize() - kHeapObjectTag;
-  adr(R0, Immediate(-entry_offset));
-  ldr(TMP, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
-  cmp(R0, Operand(TMP));
-  b(&instructions_ok, EQ);
-  brk(1);
-  Bind(&instructions_ok);
-  Pop(R0);
-#endif
-}
-
-
 void Assembler::EnterFrame(intptr_t frame_size) {
   PushPair(LR, FP);
   mov(FP, SP);
 
   if (frame_size > 0) {
     sub(SP, SP, Operand(frame_size));
   }
 }
 
 
 void Assembler::LeaveFrame() {
   mov(SP, FP);
   PopPair(LR, FP);
 }
 
 
 void Assembler::EnterDartFrame(intptr_t frame_size, Register new_pp) {
-  CheckCodePointer();
   ASSERT(!constant_pool_allowed());
   // Setup the frame.
+  adr(TMP, Immediate(-CodeSize()));  // TMP gets PC marker.
   EnterFrame(0);
-  TagAndPushPPAndPcMarker();  // Save PP and PC marker.
+  TagAndPushPPAndPcMarker(TMP);  // Save PP and PC marker.
 
   // Load the pool pointer.
   if (new_pp == kNoRegister) {
     LoadPoolPointer();
   } else {
     mov(PP, new_pp);
     set_constant_pool_allowed(true);
   }
 
   // Reserve space.
   if (frame_size > 0) {
     AddImmediate(SP, SP, -frame_size);
   }
 }
 
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate. We must also set up the pool pointer for the function.
 void Assembler::EnterOsrFrame(intptr_t extra_size, Register new_pp) {
   ASSERT(!constant_pool_allowed());
   Comment("EnterOsrFrame");
-  RestoreCodePointer();
-  LoadPoolPointer();
+  adr(TMP, Immediate(-CodeSize()));
+
+  StoreToOffset(TMP, FP, kPcMarkerSlotFromFp * kWordSize);
+
+  // Setup pool pointer for this dart function.
+  if (new_pp == kNoRegister) {
+    LoadPoolPointer();
+  } else {
+    mov(PP, new_pp);
+    set_constant_pool_allowed(true);
+  }
 
   if (extra_size > 0) {
     AddImmediate(SP, SP, -extra_size);
   }
 }
 
 
-void Assembler::LeaveDartFrame(RestorePP restore_pp) {
-  if (restore_pp == kRestoreCallerPP) {
-    set_constant_pool_allowed(false);
-    // Restore and untag PP.
-    LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize);
-    sub(PP, PP, Operand(kHeapObjectTag));
-  }
+void Assembler::LeaveDartFrame() {
+  set_constant_pool_allowed(false);
+  // Restore and untag PP.
+  LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize);
+  sub(PP, PP, Operand(kHeapObjectTag));
   LeaveFrame();
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_size) {
   EnterStubFrame();
 
   // Store fpu registers with the lowest register number at the lowest
   // address.
   for (int i = kNumberOfVRegisters - 1; i >= 0; i--) {
@@ skipping 45 matching lines @@
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry,
                             intptr_t argument_count) {
   entry.Call(this, argument_count);
 }
 
 
 void Assembler::EnterStubFrame() {
-  EnterDartFrame(0);
+  set_constant_pool_allowed(false);
+  EnterFrame(0);
+  // Save caller's pool pointer. Push 0 in the saved PC area for stub frames.
+  TagAndPushPPAndPcMarker(ZR);
+  LoadPoolPointer();
 }
 
 
 void Assembler::LeaveStubFrame() {
   LeaveDartFrame();
 }
 
 
 void Assembler::UpdateAllocationStats(intptr_t cid,
                                       Heap::Space space,
@@ skipping 224 matching lines @@
     add(base, array, Operand(index, LSL, shift));
   }
   const OperandSize size = Address::OperandSizeFor(cid);
   ASSERT(Address::CanHoldOffset(offset, Address::Offset, size));
   return Address(base, offset, Address::Offset, size);
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64