Reflow comments to use the full width.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// This file declares the TargetLoweringX86 template class, which
-/// implements the TargetLowering base interface for the x86
-/// architecture.
+/// This file declares the TargetLoweringX86 template class, which implements
+/// the TargetLowering base interface for the x86 architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 
 #include "IceDefs.h"
 #include "IceInst.h"
 #include "IceSwitchLowering.h"
 #include "IceTargetLowering.h"
@@ skipping 13 matching lines @@
 /// TargetX86Base is a template for all X86 Targets, and it relies on the CRT
 /// pattern for generating code, delegating to actual backends target-specific
 /// lowerings (e.g., call, ret, and intrinsics.) Backends are expected to
 /// implement the following methods (which should be accessible from
 /// TargetX86Base):
 ///
 /// Operand *createNaClReadTPSrcOperand()
 ///
 /// Note: Ideally, we should be able to
 ///
-///   static_assert(std::is_base_of<TargetX86Base<Machine>, Machine>::value);
+///  static_assert(std::is_base_of<TargetX86Base<Machine>, Machine>::value);
 ///
 /// but that does not work: the compiler does not know that Machine inherits
 /// from TargetX86Base at this point in translation.
 template <class Machine> class TargetX86Base : public TargetLowering {
   TargetX86Base() = delete;
   TargetX86Base(const TargetX86Base &) = delete;
   TargetX86Base &operator=(const TargetX86Base &) = delete;
 
 public:
   using Traits = MachineTraits<Machine>;
@@ skipping 41 matching lines @@
 
   const char *getConstantPrefix() const final { return "$"; }
   void emit(const ConstantUndef *C) const final;
   void emit(const ConstantInteger32 *C) const final;
   void emit(const ConstantInteger64 *C) const final;
   void emit(const ConstantFloat *C) const final;
   void emit(const ConstantDouble *C) const final;
 
   void initNodeForLowering(CfgNode *Node) override;
   /// x86-32: Ensure that a 64-bit Variable has been split into 2 32-bit
-  /// Variables, creating them if necessary.  This is needed for all
-  /// I64 operations, and it is needed for pushing F64 arguments for
-  /// function calls using the 32-bit push instruction (though the
-  /// latter could be done by directly writing to the stack).
+  /// Variables, creating them if necessary. This is needed for all I64
+  /// operations, and it is needed for pushing F64 arguments for function calls
+  /// using the 32-bit push instruction (though the latter could be done by
+  /// directly writing to the stack).
   ///
-  /// x86-64: Complains loudly if invoked because the cpu can handle
-  /// 64-bit types natively.
+  /// x86-64: Complains loudly if invoked because the cpu can handle 64-bit
+  /// types natively.
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, void>::type split64(Variable *Var);
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type split64(Variable *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (split64)");
   }
 
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, Operand>::type *
@@ skipping 106 matching lines @@
 
   using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *);
   void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
                                 Variable *Dest, Operand *Ptr, Operand *Val);
 
   void eliminateNextVectorSextInstruction(Variable *SignExtendedResult);
 
   void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest,
                            Operand *Src0, Operand *Src1);
 
-  /// Operand legalization helpers.  To deal with address mode
-  /// constraints, the helpers will create a new Operand and emit
-  /// instructions that guarantee that the Operand kind is one of those
-  /// indicated by the LegalMask (a bitmask of allowed kinds).  If the
-  /// input Operand is known to already meet the constraints, it may be
-  /// simply returned as the result, without creating any new
-  /// instructions or operands.
+  /// Operand legalization helpers. To deal with address mode constraints, the
+  /// helpers will create a new Operand and emit instructions that guarantee
+  /// that the Operand kind is one of those indicated by the LegalMask (a
+  /// bitmask of allowed kinds). If the input Operand is known to already meet
+  /// the constraints, it may be simply returned as the result, without creating
+  /// any new instructions or operands.
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0, // physical register, not stack location
     Legal_Imm = 1 << 1,
     Legal_Mem = 1 << 2, // includes [eax+4*ecx] as well as [esp+12]
     Legal_All = ~Legal_None
   };
   using LegalMask = uint32_t;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   /// Legalize the first source operand for use in the cmp instruction.
   Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
-  /// Turn a pointer operand into a memory operand that can be
-  /// used by a real load/store operation. Legalizes the operand as well.
-  /// This is a nop if the operand is already a legal memory operand.
+  /// Turn a pointer operand into a memory operand that can be used by a real
+  /// load/store operation. Legalizes the operand as well. This is a nop if the
+  /// operand is already a legal memory operand.
   typename Traits::X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
                                                     bool DoLegalize = true);
 
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
   static Type stackSlotType();
 
   static constexpr uint32_t NoSizeLimit = 0;
   static const Type TypeForSize[];
   /// Returns the largest type which is equal to or larger than Size bytes. The
-  /// type is suitable for copying memory i.e. a load and store will be a
-  /// single instruction (for example x86 will get f64 not i64).
+  /// type is suitable for copying memory i.e. a load and store will be a single
+  /// instruction (for example x86 will get f64 not i64).
   static Type largestTypeInSize(uint32_t Size, uint32_t MaxSize = NoSizeLimit);
   /// Returns the smallest type which is equal to or larger than Size bytes. If
   /// one doesn't exist then the largest type smaller than Size bytes is
   /// returned. The type is suitable for memory copies as described at
   /// largestTypeInSize.
   static Type firstTypeThatFitsSize(uint32_t Size,
                                     uint32_t MaxSize = NoSizeLimit);
 
   Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister);
 
@@ skipping 11 matching lines @@
 
   /// Return a memory operand corresponding to a stack allocated Variable.
   typename Traits::X86OperandMem *
   getMemoryOperandForStackSlot(Type Ty, Variable *Slot, uint32_t Offset = 0);
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
-  /// The following are helpers that insert lowered x86 instructions
-  /// with minimal syntactic overhead, so that the lowering code can
-  /// look as close to assembly as practical.
+  /// The following are helpers that insert lowered x86 instructions with
+  /// minimal syntactic overhead, so that the lowering code can look as close to
+  /// assembly as practical.
   void _adc(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Adc::create(Func, Dest, Src0));
   }
   void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert(Traits::Insts::AdcRMW::create(Func, DestSrc0, Src1));
   }
   void _add(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Add::create(Func, Dest, Src0));
   }
   void _add_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
@@ skipping 123 matching lines @@
   void _insertps(Variable *Dest, Operand *Src0, Operand *Src1) {
     Context.insert(Traits::Insts::Insertps::create(Func, Dest, Src0, Src1));
   }
   void _jmp(Operand *Target) {
     Context.insert(Traits::Insts::Jmp::create(Func, Target));
   }
   void _lea(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Lea::create(Func, Dest, Src0));
   }
   void _mfence() { Context.insert(Traits::Insts::Mfence::create(Func)); }
-  /// If Dest=nullptr is passed in, then a new variable is created,
-  /// marked as infinite register allocation weight, and returned
-  /// through the in/out Dest argument.
+  /// If Dest=nullptr is passed in, then a new variable is created, marked as
+  /// infinite register allocation weight, and returned through the in/out Dest
+  /// argument.
   void _mov(Variable *&Dest, Operand *Src0,
             int32_t RegNum = Variable::NoRegister) {
     if (Dest == nullptr)
       Dest = makeReg(Src0->getType(), RegNum);
     Context.insert(Traits::Insts::Mov::create(Func, Dest, Src0));
   }
   void _mov_nonkillable(Variable *Dest, Operand *Src0) {
     Inst *NewInst = Traits::Insts::Mov::create(Func, Dest, Src0);
     NewInst->setDestNonKillable();
     Context.insert(NewInst);
@@ skipping 153 matching lines @@
   }
   void _test(Operand *Src0, Operand *Src1) {
     Context.insert(Traits::Insts::Test::create(Func, Src0, Src1));
   }
   void _ucomiss(Operand *Src0, Operand *Src1) {
     Context.insert(Traits::Insts::Ucomiss::create(Func, Src0, Src1));
   }
   void _ud2() { Context.insert(Traits::Insts::UD2::create(Func)); }
   void _xadd(Operand *Dest, Variable *Src, bool Locked) {
     Context.insert(Traits::Insts::Xadd::create(Func, Dest, Src, Locked));
-    // The xadd exchanges Dest and Src (modifying Src).
-    // Model that update with a FakeDef followed by a FakeUse.
+    // The xadd exchanges Dest and Src (modifying Src). Model that update with
+    // a FakeDef followed by a FakeUse.
     Context.insert(
         InstFakeDef::create(Func, Src, llvm::dyn_cast<Variable>(Dest)));
     _set_dest_nonkillable();
     Context.insert(InstFakeUse::create(Func, Src));
   }
   void _xchg(Operand *Dest, Variable *Src) {
     Context.insert(Traits::Insts::Xchg::create(Func, Dest, Src));
     // The xchg modifies Dest and Src -- model that update with a
     // FakeDef/FakeUse.
     Context.insert(
@@ skipping 86 matching lines @@
   }
 
   BoolFolding FoldingInfo;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H