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src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 60 matching lines @@
   const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
     return RegisterAliases[Reg];
   }
   bool hasFramePointer() const override { return UsesFramePointer; }
   SizeT getFrameOrStackReg() const override {
     return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp;
   }
   SizeT getReservedTmpReg() const { return RegARM32::Reg_ip; }
 
   size_t typeWidthInBytesOnStack(Type Ty) const override {
-    // Round up to the next multiple of 4 bytes.  In particular, i1,
-    // i8, and i16 are rounded up to 4 bytes.
+    // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16
+    // are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
 
   // TODO(ascull): what size is best for ARM?
   SizeT getMinJumpTableSize() const override { return 3; }
   void emitJumpTable(const Cfg *Func,
                      const InstJumpTable *JumpTable) const override;
 
   void emitVariable(const Variable *Var) const override;
 
   const char *getConstantPrefix() const final { return "#"; }
   void emit(const ConstantUndef *C) const final;
   void emit(const ConstantInteger32 *C) const final;
   void emit(const ConstantInteger64 *C) const final;
   void emit(const ConstantFloat *C) const final;
   void emit(const ConstantDouble *C) const final;
 
   void lowerArguments() override;
   void addProlog(CfgNode *Node) override;
   void addEpilog(CfgNode *Node) override;
 
-  /// Ensure that a 64-bit Variable has been split into 2 32-bit
-  /// Variables, creating them if necessary.  This is needed for all
-  /// I64 operations.
+  /// Ensure that a 64-bit Variable has been split into 2 32-bit Variables,
+  /// creating them if necessary. This is needed for all I64 operations.
   void split64(Variable *Var);
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
                               size_t BasicFrameOffset, size_t &InArgsSizeBytes);
 
   bool hasCPUFeature(TargetARM32Features::ARM32InstructionSet I) const {
     return CPUFeatures.hasFeature(I);
   }
   Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
@@ skipping 23 matching lines @@
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void prelowerPhis() override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0,  /// physical register, not stack location
-    Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated
-                         /// small immediates, or shifted registers.
+    Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
+                         /// immediates, or shifted registers.
     Legal_Mem = 1 << 2,  /// includes [r0, r1 lsl #2] as well as [sp, #12]
     Legal_All = ~Legal_None
   };
   using LegalMask = uint32_t;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
   static Type stackSlotType();
   Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister);
   void alignRegisterPow2(Variable *Reg, uint32_t Align);
 
   /// Returns a vector in a register with the given constant entries.
   Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister);
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
-  // If a divide-by-zero check is needed, inserts a:
-  // test; branch .LSKIP; trap; .LSKIP: <continuation>.
-  // If no check is needed nothing is inserted.
+  // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap;
+  // .LSKIP: <continuation>. If no check is needed nothing is inserted.
   void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
   using ExtInstr = void (TargetARM32::*)(Variable *, Variable *,
                                          CondARM32::Cond);
   using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *,
                                          CondARM32::Cond);
   void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1,
                     ExtInstr ExtFunc, DivInstr DivFunc,
                     const char *DivHelperName, bool IsRemainder);
 
   void lowerCLZ(Variable *Dest, Variable *ValLo, Variable *ValHi);
 
-  // The following are helpers that insert lowered ARM32 instructions
-  // with minimal syntactic overhead, so that the lowering code can
-  // look as close to assembly as practical.
+  // The following are helpers that insert lowered ARM32 instructions with
+  // minimal syntactic overhead, so that the lowering code can look as close to
+  // assembly as practical.
 
   void _add(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, Pred));
   }
   void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
@@ skipping 57 matching lines @@
     Context.insert(InstARM32Lsr::create(Func, Dest, Src0, Src1, Pred));
   }
   void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc, Pred));
   }
   void _mls(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Mls::create(Func, Dest, Src0, Src1, Acc, Pred));
   }
-  /// If Dest=nullptr is passed in, then a new variable is created,
-  /// marked as infinite register allocation weight, and returned
-  /// through the in/out Dest argument.
+  /// If Dest=nullptr is passed in, then a new variable is created, marked as
+  /// infinite register allocation weight, and returned through the in/out Dest
+  /// argument.
   void _mov(Variable *&Dest, Operand *Src0,
             CondARM32::Cond Pred = CondARM32::AL,
             int32_t RegNum = Variable::NoRegister) {
     if (Dest == nullptr)
       Dest = makeReg(Src0->getType(), RegNum);
     Context.insert(InstARM32Mov::create(Func, Dest, Src0, Pred));
   }
   void _mov_nonkillable(Variable *Dest, Operand *Src0,
                         CondARM32::Cond Pred = CondARM32::AL) {
     Inst *NewInst = InstARM32Mov::create(Func, Dest, Src0, Pred);
     NewInst->setDestNonKillable();
     Context.insert(NewInst);
   }
-  /// The Operand can only be a 16-bit immediate or a ConstantRelocatable
-  /// (with an upper16 relocation).
+  /// The Operand can only be a 16-bit immediate or a ConstantRelocatable (with
+  /// an upper16 relocation).
   void _movt(Variable *Dest, Operand *Src0,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Movt::create(Func, Dest, Src0, Pred));
   }
   void _movw(Variable *Dest, Operand *Src0,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Movw::create(Func, Dest, Src0, Pred));
   }
   void _mul(Variable *Dest, Variable *Src0, Variable *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
@@ skipping 75 matching lines @@
   }
   void _trap() { Context.insert(InstARM32Trap::create(Func)); }
   void _udiv(Variable *Dest, Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Udiv::create(Func, Dest, Src0, Src1, Pred));
   }
   void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
               Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(
         InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred));
-    // Model the modification to the second dest as a fake def.
-    // Note that the def is not predicated.
+    // Model the modification to the second dest as a fake def. Note that the
+    // def is not predicated.
     Context.insert(InstFakeDef::create(Func, DestHi, DestLo));
   }
   void _uxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Uxt::create(Func, Dest, Src0, Pred));
   }
   void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vadd::create(Func, Dest, Src0, Src1));
   }
   void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vcvt::create(Func, Dest, Src, Variant, Pred));
   }
   void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vdiv::create(Func, Dest, Src0, Src1));
   }
   void _vldr(Variable *Dest, OperandARM32Mem *Src,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vldr::create(Func, Dest, Src, Pred));
   }
-  // There are a whole bunch of vmov variants, to transfer within
-  // S/D/Q registers, between core integer registers and S/D,
-  // and from small immediates into S/D.
-  // For integer -> S/D/Q there is a variant which takes two integer
-  // register to fill a D, or to fill two consecutive S registers.
+  // There are a whole bunch of vmov variants, to transfer within S/D/Q
+  // registers, between core integer registers and S/D, and from small
+  // immediates into S/D. For integer -> S/D/Q there is a variant which takes
+  // two integer register to fill a D, or to fill two consecutive S registers.
   // Vmov can also be used to insert-element. E.g.,
   //    "vmov.8 d0[1], r0"
   // but insert-element is a "two-address" operation where only part of the
   // register is modified. This cannot model that.
   //
   // This represents the simple single source, single dest variants only.
   void _vmov(Variable *Dest, Operand *Src0) {
     constexpr CondARM32::Cond Pred = CondARM32::AL;
     Context.insert(InstARM32Vmov::create(Func, Dest, Src0, Pred));
   }
@@ skipping 15 matching lines @@
   }
   void _vsqrt(Variable *Dest, Variable *Src,
               CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
   }
   void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
 
   /// Run a pass through stack variables and ensure that the offsets are legal.
-  /// If the offset is not legal, use a new base register that accounts for
-  /// the offset, such that the addressing mode offset bits are now legal.
+  /// If the offset is not legal, use a new base register that accounts for the
+  /// offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
   /// Returns true if the given Offset can be represented in a stack ldr/str.
   bool isLegalVariableStackOffset(int32_t Offset) const;
   /// Assuming Var needs its offset legalized, define a new base register
   /// centered on the given Var's offset and use it.
   StackVariable *legalizeVariableSlot(Variable *Var, Variable *OrigBaseReg);
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,
   /// regardless of their position relative to the floating-point/vector
-  /// arguments in the argument list. Floating-point and vector arguments
-  /// can use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can
-  /// start with registers but extend beyond the available registers can be
-  /// split between the registers and the stack. However, this is typically
-  /// for passing GPR structs by value, and PNaCl transforms expand this out.
+  /// arguments in the argument list. Floating-point and vector arguments can
+  /// use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can start with
+  /// registers but extend beyond the available registers can be split between
+  /// the registers and the stack. However, this is typically for passing GPR
+  /// structs by value, and PNaCl transforms expand this out.
   ///
   /// Also, at the point before the call, the stack must be aligned.
   class CallingConv {
     CallingConv(const CallingConv &) = delete;
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
     CallingConv() {}
     ~CallingConv() = default;
 
@@ skipping 54 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H