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| 1 //===- subzero/src/IceRegistersX8632.h - Register information ---*- C++ -*-===// | 1 //===- subzero/src/IceRegistersX8632.h - Register information ---*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| 11 /// This file declares the registers and their encodings for x86-32. | 11 /// This file declares the registers and their encodings for x86-32. |
| 12 /// | 12 /// |
| 13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
| 14 | 14 |
| 15 #ifndef SUBZERO_SRC_ICEREGISTERSX8632_H | 15 #ifndef SUBZERO_SRC_ICEREGISTERSX8632_H |
| 16 #define SUBZERO_SRC_ICEREGISTERSX8632_H | 16 #define SUBZERO_SRC_ICEREGISTERSX8632_H |
| 17 | 17 |
| 18 #include "IceDefs.h" | 18 #include "IceDefs.h" |
| 19 #include "IceInstX8632.def" | 19 #include "IceInstX8632.def" |
| 20 #include "IceTypes.h" | 20 #include "IceTypes.h" |
| 21 | 21 |
| 22 namespace Ice { | 22 namespace Ice { |
| 23 | 23 |
| 24 class RegX8632 { | 24 class RegX8632 { |
| 25 public: | 25 public: |
| 26 /// An enum of every register. The enum value may not match the encoding | 26 /// An enum of every register. The enum value may not match the encoding used |
| 27 /// used to binary encode register operands in instructions. | 27 /// to binary encode register operands in instructions. |
| 28 enum AllRegisters { | 28 enum AllRegisters { |
| 29 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 29 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 30 frameptr, isI8, isInt, isFP) \ | 30 frameptr, isI8, isInt, isFP) \ |
| 31 val, | 31 val, |
| 32 REGX8632_TABLE | 32 REGX8632_TABLE |
| 33 #undef X | 33 #undef X |
| 34 Reg_NUM, | 34 Reg_NUM, |
| 35 #define X(val, init) val init, | 35 #define X(val, init) val init, |
| 36 REGX8632_TABLE_BOUNDS | 36 REGX8632_TABLE_BOUNDS |
| 37 #undef X | 37 #undef X |
| 38 }; | 38 }; |
| 39 | 39 |
| 40 /// An enum of GPR Registers. The enum value does match the encoding used | 40 /// An enum of GPR Registers. The enum value does match the encoding used to |
| 41 /// to binary encode register operands in instructions. | 41 /// binary encode register operands in instructions. |
| 42 enum GPRRegister { | 42 enum GPRRegister { |
| 43 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 43 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 44 frameptr, isI8, isInt, isFP) \ | 44 frameptr, isI8, isInt, isFP) \ |
| 45 Encoded_##val = encode, | 45 Encoded_##val = encode, |
| 46 REGX8632_GPR_TABLE | 46 REGX8632_GPR_TABLE |
| 47 #undef X | 47 #undef X |
| 48 Encoded_Not_GPR = -1 | 48 Encoded_Not_GPR = -1 |
| 49 }; | 49 }; |
| 50 | 50 |
| 51 /// An enum of XMM Registers. The enum value does match the encoding used | 51 /// An enum of XMM Registers. The enum value does match the encoding used to |
| 52 /// to binary encode register operands in instructions. | 52 /// binary encode register operands in instructions. |
| 53 enum XmmRegister { | 53 enum XmmRegister { |
| 54 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 54 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 55 frameptr, isI8, isInt, isFP) \ | 55 frameptr, isI8, isInt, isFP) \ |
| 56 Encoded_##val = encode, | 56 Encoded_##val = encode, |
| 57 REGX8632_XMM_TABLE | 57 REGX8632_XMM_TABLE |
| 58 #undef X | 58 #undef X |
| 59 Encoded_Not_Xmm = -1 | 59 Encoded_Not_Xmm = -1 |
| 60 }; | 60 }; |
| 61 | 61 |
| 62 /// An enum of Byte Registers. The enum value does match the encoding used | 62 /// An enum of Byte Registers. The enum value does match the encoding used to |
| 63 /// to binary encode register operands in instructions. | 63 /// binary encode register operands in instructions. |
| 64 enum ByteRegister { | 64 enum ByteRegister { |
| 65 #define X(val, encode) Encoded_##val encode, | 65 #define X(val, encode) Encoded_##val encode, |
| 66 REGX8632_BYTEREG_TABLE | 66 REGX8632_BYTEREG_TABLE |
| 67 #undef X | 67 #undef X |
| 68 Encoded_Not_ByteReg = -1 | 68 Encoded_Not_ByteReg = -1 |
| 69 }; | 69 }; |
| 70 | 70 |
| 71 /// An enum of X87 Stack Registers. The enum value does match the encoding | 71 /// An enum of X87 Stack Registers. The enum value does match the encoding |
| 72 /// used to binary encode register operands in instructions. | 72 /// used to binary encode register operands in instructions. |
| 73 enum X87STRegister { | 73 enum X87STRegister { |
| (...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 105 static inline X87STRegister getEncodedSTReg(int32_t RegNum) { | 105 static inline X87STRegister getEncodedSTReg(int32_t RegNum) { |
| 106 assert(Encoded_X87ST_First <= RegNum); | 106 assert(Encoded_X87ST_First <= RegNum); |
| 107 assert(RegNum <= Encoded_X87ST_Last); | 107 assert(RegNum <= Encoded_X87ST_Last); |
| 108 return X87STRegister(RegNum); | 108 return X87STRegister(RegNum); |
| 109 } | 109 } |
| 110 }; | 110 }; |
| 111 | 111 |
| 112 } // end of namespace Ice | 112 } // end of namespace Ice |
| 113 | 113 |
| 114 #endif // SUBZERO_SRC_ICEREGISTERSX8632_H | 114 #endif // SUBZERO_SRC_ICEREGISTERSX8632_H |
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