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1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// | 1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
11 /// This file declares the registers and their encodings for ARM32. | 11 /// This file declares the registers and their encodings for ARM32. |
12 /// | 12 /// |
13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
14 | 14 |
15 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H | 15 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H |
16 #define SUBZERO_SRC_ICEREGISTERSARM32_H | 16 #define SUBZERO_SRC_ICEREGISTERSARM32_H |
17 | 17 |
18 #include "IceDefs.h" | 18 #include "IceDefs.h" |
19 #include "IceInstARM32.def" | 19 #include "IceInstARM32.def" |
20 #include "IceTypes.h" | 20 #include "IceTypes.h" |
21 | 21 |
22 namespace Ice { | 22 namespace Ice { |
23 | 23 |
24 class RegARM32 { | 24 class RegARM32 { |
25 public: | 25 public: |
26 /// An enum of every register. The enum value may not match the encoding | 26 /// An enum of every register. The enum value may not match the encoding used |
27 /// used to binary encode register operands in instructions. | 27 /// to binary encode register operands in instructions. |
28 enum AllRegisters { | 28 enum AllRegisters { |
29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
30 isFP32, isFP64, isVec128, alias_init) \ | 30 isFP32, isFP64, isVec128, alias_init) \ |
31 val, | 31 val, |
32 REGARM32_TABLE | 32 REGARM32_TABLE |
33 #undef X | 33 #undef X |
34 Reg_NUM, | 34 Reg_NUM, |
35 #define X(val, init) val init, | 35 #define X(val, init) val init, |
36 REGARM32_TABLE_BOUNDS | 36 REGARM32_TABLE_BOUNDS |
37 #undef X | 37 #undef X |
38 }; | 38 }; |
39 | 39 |
40 /// An enum of GPR Registers. The enum value does match the encoding used | 40 /// An enum of GPR Registers. The enum value does match the encoding used to |
41 /// to binary encode register operands in instructions. | 41 /// binary encode register operands in instructions. |
42 enum GPRRegister { | 42 enum GPRRegister { |
43 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 43 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
44 isFP32, isFP64, isVec128, alias_init) \ | 44 isFP32, isFP64, isVec128, alias_init) \ |
45 Encoded_##val = encode, | 45 Encoded_##val = encode, |
46 REGARM32_GPR_TABLE | 46 REGARM32_GPR_TABLE |
47 #undef X | 47 #undef X |
48 Encoded_Not_GPR = -1 | 48 Encoded_Not_GPR = -1 |
49 }; | 49 }; |
50 | 50 |
51 /// An enum of FP32 S-Registers. The enum value does match the encoding used | 51 /// An enum of FP32 S-Registers. The enum value does match the encoding used |
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102 static inline QRegister getEncodedQReg(int32_t RegNum) { | 102 static inline QRegister getEncodedQReg(int32_t RegNum) { |
103 assert(Reg_QREG_First <= RegNum); | 103 assert(Reg_QREG_First <= RegNum); |
104 assert(RegNum <= Reg_QREG_Last); | 104 assert(RegNum <= Reg_QREG_Last); |
105 return QRegister(RegNum - Reg_QREG_First); | 105 return QRegister(RegNum - Reg_QREG_First); |
106 } | 106 } |
107 }; | 107 }; |
108 | 108 |
109 } // end of namespace Ice | 109 } // end of namespace Ice |
110 | 110 |
111 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H | 111 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H |
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