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src/IceRegAlloc.h

 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 42 matching lines @@
     int32_t PreferReg = Variable::NoRegister;
     bool AllowOverlap = false;
     llvm::SmallBitVector RegMask;
     llvm::SmallBitVector Free;
     llvm::SmallBitVector PrecoloredUnhandledMask; // Note: only used for dumping
     llvm::SmallVector<RegWeight, REGS_SIZE> Weights;
   };
 
   void initForGlobal();
   void initForInfOnly();
-  /// Move an item from the From set to the To set.  From[Index] is pushed onto
+  /// Move an item from the From set to the To set. From[Index] is pushed onto
   /// the end of To[], then the item is efficiently removed from From[] by
   /// effectively swapping it with the last item in From[] and then popping it
-  /// from the back.  As such, the caller is best off iterating over From[] in
+  /// from the back. As such, the caller is best off iterating over From[] in
   /// reverse order to avoid the need for special handling of the iterator.
   void moveItem(UnorderedRanges &From, SizeT Index, UnorderedRanges &To) {
     To.push_back(From[Index]);
     From[Index] = From.back();
     From.pop_back();
   }
 
   /// \name scan helper functions.
   /// @{
   /// Free up a register for infinite-weight Cur by spilling and reloading some
@@ skipping 25 matching lines @@
   /// UnhandledPrecolored is a subset of Unhandled, specially collected for
   /// faster processing.
   OrderedRanges UnhandledPrecolored;
   UnorderedRanges Active, Inactive, Handled;
   std::vector<InstNumberT> Kills;
   RegAllocKind Kind = RAK_Unknown;
   /// RegUses[I] is the number of live ranges (variables) that register I is
   /// currently assigned to. It can be greater than 1 as a result of
   /// AllowOverlap inference.
   llvm::SmallVector<int32_t, REGS_SIZE> RegUses;
-  // TODO(jpp): for some architectures a SmallBitVector might not be big enough.
-  // Evaluate what the performance impact on those architectures is.
+  // TODO(jpp): for some architectures a SmallBitVector might not be big
+  // enough. Evaluate what the performance impact on those architectures is.
   llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases;
   bool FindPreference = false;
   bool FindOverlap = false;
 
   const bool Verbose;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGALLOC_H