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src/IceRegAlloc.cpp

 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 64 matching lines @@
   Var->dump(Func);
   Str << "  Range=" << Var->getLiveRange();
 }
 
 } // end of anonymous namespace
 
 LinearScan::LinearScan(Cfg *Func)
     : Func(Func), Ctx(Func->getContext()), Target(Func->getTarget()),
       Verbose(BuildDefs::dump() && Func->isVerbose(IceV_LinearScan)) {}
 
-// Prepare for full register allocation of all variables.  We depend on
-// liveness analysis to have calculated live ranges.
+// Prepare for full register allocation of all variables. We depend on liveness
+// analysis to have calculated live ranges.
 void LinearScan::initForGlobal() {
   TimerMarker T(TimerStack::TT_initUnhandled, Func);
   FindPreference = true;
   // For full register allocation, normally we want to enable FindOverlap
   // (meaning we look for opportunities for two overlapping live ranges to
-  // safely share the same register).  However, we disable it for phi-lowering
+  // safely share the same register). However, we disable it for phi-lowering
   // register allocation since no overlap opportunities should be available and
   // it's more expensive to look for opportunities.
   FindOverlap = (Kind != RAK_Phi);
   const VarList &Vars = Func->getVariables();
   Unhandled.reserve(Vars.size());
   UnhandledPrecolored.reserve(Vars.size());
   // Gather the live ranges of all variables and add them to the Unhandled set.
   for (Variable *Var : Vars) {
     // Explicitly don't consider zero-weight variables, which are meant to be
     // spill slots.
@@ skipping 152 matching lines @@
   std::sort(Unhandled.rbegin(), Unhandled.rend(), CompareRanges);
   std::sort(UnhandledPrecolored.rbegin(), UnhandledPrecolored.rend(),
             CompareRanges);
 
   Handled.reserve(Unhandled.size());
   Inactive.reserve(Unhandled.size());
   Active.reserve(Unhandled.size());
 }
 
 // This is called when Cur must be allocated a register but no registers are
-// available across Cur's live range.  To handle this, we find a register that
+// available across Cur's live range. To handle this, we find a register that
 // is not explicitly used during Cur's live range, spill that register to a
 // stack location right before Cur's live range begins, and fill (reload) the
 // register from the stack location right after Cur's live range ends.
 void LinearScan::addSpillFill(IterationState &Iter) {
   // Identify the actual instructions that begin and end Iter.Cur's live range.
   // Iterate through Iter.Cur's node's instruction list until we find the actual
   // instructions with instruction numbers corresponding to Iter.Cur's recorded
   // live range endpoints.  This sounds inefficient but shouldn't be a problem
   // in practice because:
   // (1) This function is almost never called in practice.
@@ skipping 14 matching lines @@
   InstList::iterator SpillPoint = Insts.end();
   InstList::iterator FillPoint = Insts.end();
   // Stop searching after we have found both the SpillPoint and the FillPoint.
   for (auto I = Insts.begin(), E = Insts.end();
        I != E && (SpillPoint == E || FillPoint == E); ++I) {
     if (I->getNumber() == Start)
       SpillPoint = I;
     if (I->getNumber() == End)
       FillPoint = I;
     if (SpillPoint != E) {
-      // Remove from RegMask any physical registers referenced during Cur's live
-      // range.  Start looking after SpillPoint gets set, i.e. once Cur's live
-      // range begins.
+      // Remove from RegMask any physical registers referenced during Cur's
+      // live range. Start looking after SpillPoint gets set, i.e. once Cur's
+      // live range begins.
       FOREACH_VAR_IN_INST(Var, *I) {
         if (!Var->hasRegTmp())
           continue;
         const llvm::SmallBitVector &Aliases = *RegAliases[Var->getRegNumTmp()];
         for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
              RegAlias = Aliases.find_next(RegAlias)) {
           Iter.RegMask[RegAlias] = false;
         }
       }
     }
   }
   assert(SpillPoint != Insts.end());
   assert(FillPoint != Insts.end());
   ++FillPoint;
   // TODO(stichnot): Randomize instead of find_first().
   int32_t RegNum = Iter.RegMask.find_first();
   assert(RegNum != -1);
   Iter.Cur->setRegNumTmp(RegNum);
   Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType());
-  // TODO(stichnot): Add SpillLoc to VariablesMetadata tracking so that SpillLoc
-  // is correctly identified as !isMultiBlock(), reducing stack frame size.
+  // TODO(stichnot): Add SpillLoc to VariablesMetadata tracking so that
+  // SpillLoc is correctly identified as !isMultiBlock(), reducing stack frame
+  // size.
   Variable *SpillLoc = Func->makeVariable(Iter.Cur->getType());
   // Add "reg=FakeDef;spill=reg" before SpillPoint
   Target->lowerInst(Node, SpillPoint, InstFakeDef::create(Func, Preg));
   Target->lowerInst(Node, SpillPoint, InstAssign::create(Func, SpillLoc, Preg));
   // add "reg=spill;FakeUse(reg)" before FillPoint
   Target->lowerInst(Node, FillPoint, InstAssign::create(Func, Preg, SpillLoc));
   Target->lowerInst(Node, FillPoint, InstFakeUse::create(Func, Preg));
 }
 
 void LinearScan::handleActiveRangeExpiredOrInactive(const Variable *Cur) {
@@ skipping 72 matching lines @@
       bool IsAssign = DefInst->isSimpleAssign();
       bool IsSingleDef = !VMetadata->isMultiDef(Iter.Cur);
       for (SizeT i = 0; i < DefInst->getSrcSize(); ++i) {
         // TODO(stichnot): Iterate through the actual Variables of the
         // instruction, not just the source operands. This could capture Load
         // instructions, including address mode optimization, for Prefer (but
         // not for AllowOverlap).
         if (Variable *SrcVar = llvm::dyn_cast<Variable>(DefInst->getSrc(i))) {
           int32_t SrcReg = SrcVar->getRegNumTmp();
           // Only consider source variables that have (so far) been assigned a
-          // register. That register must be one in the RegMask set, e.g.
-          // don't try to prefer the stack pointer as a result of the stacksave
+          // register. That register must be one in the RegMask set, e.g. don't
+          // try to prefer the stack pointer as a result of the stacksave
           // intrinsic.
           if (SrcVar->hasRegTmp() && Iter.RegMask[SrcReg]) {
             if (FindOverlap && !Iter.Free[SrcReg]) {
               // Don't bother trying to enable AllowOverlap if the register is
               // already free.
               Iter.AllowOverlap = IsSingleDef && IsAssign &&
                                   !overlapsDefs(Func, Iter.Cur, SrcVar);
             }
             if (Iter.AllowOverlap || Iter.Free[SrcReg]) {
               Iter.Prefer = SrcVar;
@@ skipping 34 matching lines @@
           RegAlias == Iter.PreferReg && overlapsDefs(Func, Iter.Cur, Item)) {
         Iter.AllowOverlap = false;
         dumpDisableOverlap(Func, Item, "Inactive");
       }
     }
   }
 }
 
 // Remove registers from the Free[] list where an Unhandled pre-colored range
 // overlaps with the current range, and set those registers to infinite weight
-// so that they aren't candidates for eviction.  Cur->rangeEndsBefore(Item) is
+// so that they aren't candidates for eviction. Cur->rangeEndsBefore(Item) is
 // an early exit check that turns a guaranteed O(N^2) algorithm into expected
 // linear complexity.
 void LinearScan::filterFreeWithPrecoloredRanges(IterationState &Iter) {
   for (Variable *Item : reverse_range(UnhandledPrecolored)) {
     assert(Item->hasReg());
     if (Iter.Cur->rangeEndsBefore(Item))
       break;
     if (Item->rangeOverlaps(Iter.Cur)) {
       const llvm::SmallBitVector &Aliases =
           *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp()
@@ skipping 120 matching lines @@
         }
         Item->setRegNumTmp(Variable::NoRegister);
         moveItem(Active, Index, Handled);
       }
     }
     // Do the same for Inactive.
     for (SizeT I = Inactive.size(); I > 0; --I) {
       const SizeT Index = I - 1;
       Variable *Item = Inactive[Index];
       // Note: The Item->rangeOverlaps(Cur) clause is not part of the
-      // description of AssignMemLoc() in the original paper.  But there
-      // doesn't seem to be any need to evict an inactive live range that
-      // doesn't overlap with the live range currently being considered. It's
+      // description of AssignMemLoc() in the original paper. But there doesn't
+      // seem to be any need to evict an inactive live range that doesn't
+      // overlap with the live range currently being considered. It's
       // especially bad if we would end up evicting an infinite-weight but
       // currently-inactive live range. The most common situation for this
       // would be a scratch register kill set for call instructions.
       if (Item->getRegNumTmp() == MinWeightIndex &&
           Item->rangeOverlaps(Iter.Cur)) {
         dumpLiveRangeTrace("Evicting     ", Item);
         Item->setRegNumTmp(Variable::NoRegister);
         moveItem(Inactive, Index, Handled);
       }
     }
@@ skipping 11 matching lines @@
 }
 
 void LinearScan::assignFinalRegisters(
     const llvm::SmallBitVector &RegMaskFull,
     const llvm::SmallBitVector &PreDefinedRegisters, bool Randomized) {
   const size_t NumRegisters = RegMaskFull.size();
   llvm::SmallVector<int32_t, REGS_SIZE> Permutation(NumRegisters);
   if (Randomized) {
     // Create a random number generator for regalloc randomization. Merge
     // function's sequence and Kind value as the Salt. Because regAlloc() is
-    // called twice under O2, the second time with RAK_Phi, we check
-    // Kind == RAK_Phi to determine the lowest-order bit to make sure the Salt
-    // is different.
+    // called twice under O2, the second time with RAK_Phi, we check Kind ==
+    // RAK_Phi to determine the lowest-order bit to make sure the Salt is
+    // different.
     uint64_t Salt =
         (Func->getSequenceNumber() << 1) ^ (Kind == RAK_Phi ? 0u : 1u);
     Target->makeRandomRegisterPermutation(
         Permutation, PreDefinedRegisters | ~RegMaskFull, Salt);
   }
 
   // Finish up by setting RegNum = RegNumTmp (or a random permutation thereof)
   // for each Variable.
   for (Variable *Item : Handled) {
     int32_t RegNum = Item->getRegNumTmp();
@@ skipping 222 matching lines @@
     Str << "\n";
   }
   Str << "++++++ Inactive:\n";
   for (const Variable *Item : Inactive) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 } // end of namespace Ice