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src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 94 matching lines @@
 InstX86Br<Machine>::InstX86Br(
     Cfg *Func, const CfgNode *TargetTrue, const CfgNode *TargetFalse,
     const InstX86Label<Machine> *Label,
     typename InstX86Base<Machine>::Traits::Cond::BrCond Condition, Mode Kind)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Br, 0, nullptr),
       Condition(Condition), TargetTrue(TargetTrue), TargetFalse(TargetFalse),
       Label(Label), Kind(Kind) {}
 
 template <class Machine>
 bool InstX86Br<Machine>::optimizeBranch(const CfgNode *NextNode) {
-  // If there is no next block, then there can be no fallthrough to
-  // optimize.
+  // If there is no next block, then there can be no fallthrough to optimize.
   if (NextNode == nullptr)
     return false;
   // Intra-block conditional branches can't be optimized.
   if (Label)
     return false;
-  // If there is no fallthrough node, such as a non-default case label
-  // for a switch instruction, then there is no opportunity to
-  // optimize.
+  // If there is no fallthrough node, such as a non-default case label for a
+  // switch instruction, then there is no opportunity to optimize.
   if (getTargetFalse() == nullptr)
     return false;
 
   // Unconditional branch to the next node can be removed.
   if (Condition == InstX86Base<Machine>::Traits::Cond::Br_None &&
       getTargetFalse() == NextNode) {
     assert(getTargetTrue() == nullptr);
     this->setDeleted();
     return true;
   }
-  // If the fallthrough is to the next node, set fallthrough to nullptr
-  // to indicate.
+  // If the fallthrough is to the next node, set fallthrough to nullptr to
+  // indicate.
   if (getTargetFalse() == NextNode) {
     TargetFalse = nullptr;
     return true;
   }
-  // If TargetTrue is the next node, and TargetFalse is not nullptr
-  // (which was already tested above), then invert the branch
-  // condition, swap the targets, and set new fallthrough to nullptr.
+  // If TargetTrue is the next node, and TargetFalse is not nullptr (which was
+  // already tested above), then invert the branch condition, swap the targets,
+  // and set new fallthrough to nullptr.
   if (getTargetTrue() == NextNode) {
     assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
     Condition = this->getOppositeCondition(Condition);
     TargetTrue = getTargetFalse();
     TargetFalse = nullptr;
     return true;
   }
   return false;
 }
 
@@ skipping 24 matching lines @@
   this->HasSideEffects = true;
   this->addSource(CallTarget);
 }
 
 template <class Machine>
 InstX86Cmov<Machine>::InstX86Cmov(
     Cfg *Func, Variable *Dest, Operand *Source,
     typename InstX86Base<Machine>::Traits::Cond::BrCond Condition)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Cmov, 2, Dest),
       Condition(Condition) {
-  // The final result is either the original Dest, or Source, so mark
-  // both as sources.
+  // The final result is either the original Dest, or Source, so mark both as
+  // sources.
   this->addSource(Dest);
   this->addSource(Source);
 }
 
 template <class Machine>
 InstX86Cmpps<Machine>::InstX86Cmpps(
     Cfg *Func, Variable *Dest, Operand *Source,
     typename InstX86Base<Machine>::Traits::Cond::CmppsCond Condition)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Cmpps, 2, Dest),
       Condition(Condition) {
@@ skipping 113 matching lines @@
   this->addSource(Src);
 }
 
 template <class Machine>
 InstX86Fstp<Machine>::InstX86Fstp(Cfg *Func, Variable *Dest)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Fstp, 0, Dest) {}
 
 template <class Machine>
 InstX86Pop<Machine>::InstX86Pop(Cfg *Func, Variable *Dest)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Pop, 0, Dest) {
-  // A pop instruction affects the stack pointer and so it should not
-  // be allowed to be automatically dead-code eliminated.  (The
-  // corresponding push instruction doesn't need this treatment
-  // because it has no dest variable and therefore won't be dead-code
-  // eliminated.)  This is needed for late-stage liveness analysis
-  // (e.g. asm-verbose mode).
+  // A pop instruction affects the stack pointer and so it should not be
+  // allowed to be automatically dead-code eliminated. (The corresponding push
+  // instruction doesn't need this treatment because it has no dest variable
+  // and therefore won't be dead-code eliminated.) This is needed for
+  // late-stage liveness analysis (e.g. asm-verbose mode).
   this->HasSideEffects = true;
 }
 
 template <class Machine>
 InstX86Push<Machine>::InstX86Push(Cfg *Func, Variable *Source)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Push, 1, nullptr) {
   this->addSource(Source);
 }
 
 template <class Machine>
@@ skipping 183 matching lines @@
 void InstX86Jmp<Machine>::emitIAS(const Cfg *Func) const {
   // Note: Adapted (mostly copied) from InstX86Call<Machine>::emitIAS().
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Operand *Target = getJmpTarget();
   if (const auto Var = llvm::dyn_cast<Variable>(Target)) {
     if (Var->hasReg()) {
       Asm->jmp(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
           Var->getRegNum()));
     } else {
-      // The jmp instruction with a memory operand should be possible
-      // to encode, but it isn't a valid sandboxed instruction, and
-      // there shouldn't be a register allocation issue to jump
-      // through a scratch register, so we don't really need to bother
-      // implementing it.
+      // The jmp instruction with a memory operand should be possible to
+      // encode, but it isn't a valid sandboxed instruction, and there
+      // shouldn't be a register allocation issue to jump through a scratch
+      // register, so we don't really need to bother implementing it.
       llvm::report_fatal_error("Assembler can't jmp to memory operand");
     }
   } else if (const auto Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(
                  Target)) {
     (void)Mem;
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     llvm::report_fatal_error("Assembler can't jmp to memory operand");
   } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
     assert(CR->getOffset() == 0 && "We only support jumping to a function");
     Asm->jmp(CR);
   } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
     // NaCl trampoline calls refer to an address within the sandbox directly.
-    // This is usually only needed for non-IRT builds and otherwise not
-    // very portable or stable. Usually this is only done for "calls"
-    // and not jumps.
-    // TODO(jvoung): Support this when there is a lowering that
-    // actually triggers this case.
+    // This is usually only needed for non-IRT builds and otherwise not very
+    // portable or stable. Usually this is only done for "calls" and not jumps.
+    // TODO(jvoung): Support this when there is a lowering that actually
+    // triggers this case.
     (void)Imm;
     llvm::report_fatal_error("Unexpected jmp to absolute address");
   } else {
     llvm::report_fatal_error("Unexpected operand type");
   }
 }
 
 template <class Machine> void InstX86Jmp<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 60 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->getDest()) {
     this->dumpDest(Func);
     Str << " = ";
   }
   Str << "call ";
   getCallTarget()->dump(Func);
 }
 
-// The ShiftHack parameter is used to emit "cl" instead of "ecx" for
-// shift instructions, in order to be syntactically valid.  The
-// this->Opcode parameter needs to be char* and not IceString because of
-// template issues.
+// The ShiftHack parameter is used to emit "cl" instead of "ecx" for shift
+// instructions, in order to be syntactically valid. The this->Opcode parameter
+// needs to be char* and not IceString because of template issues.
 template <class Machine>
 void InstX86Base<Machine>::emitTwoAddress(const char *Opcode, const Inst *Inst,
                                           const Cfg *Func, bool ShiftHack) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Operand *Dest = Inst->getDest();
   if (Dest == nullptr)
     Dest = Inst->getSrc(0);
@@ skipping 145 matching lines @@
   }
 }
 
 template <class Machine>
 void InstX86Base<Machine>::emitIASGPRShift(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterShiftOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
-  // Technically, the Dest Var can be mem as well, but we only use Reg.
-  // We can extend this to check Dest if we decide to use that form.
+  // Technically, the Dest Var can be mem as well, but we only use Reg. We can
+  // extend this to check Dest if we decide to use that form.
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
       InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
           Ty, Var->getRegNum());
-  // Src must be reg == ECX or an Imm8.
-  // This is asserted by the assembler.
+  // Src must be reg == ECX or an Imm8. This is asserted by the assembler.
   if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
             Ty, SrcVar->getRegNum());
     (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
   } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
@@ skipping 506 matching lines @@
     (void)Src0Var;
     assert(Src0Var &&
            Src0Var->getRegNum() ==
                InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
     static const typename InstX86Base<
         Machine>::Traits::Assembler::GPREmitterOneOp Emitter = {
         &InstX86Base<Machine>::Traits::Assembler::imul,
         &InstX86Base<Machine>::Traits::Assembler::imul};
     emitIASOpTyGPR<Machine>(Func, Ty, this->getSrc(1), Emitter);
   } else {
-    // We only use imul as a two-address instruction even though
-    // there is a 3 operand version when one of the operands is a constant.
+    // We only use imul as a two-address instruction even though there is a 3
+    // operand version when one of the operands is a constant.
     assert(Var == this->getSrc(0));
     static const typename InstX86Base<
         Machine>::Traits::Assembler::GPREmitterRegOp Emitter = {
         &InstX86Base<Machine>::Traits::Assembler::imul,
         &InstX86Base<Machine>::Traits::Assembler::imul,
         &InstX86Base<Machine>::Traits::Assembler::imul};
     emitIASRegOpTyGPR<Machine>(Func, Ty, Var, Src, Emitter);
   }
 }
 
@@ skipping 319 matching lines @@
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Cmpps<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
   assert(Condition < InstX86Base<Machine>::Traits::Cond::Cmpps_Invalid);
-  // Assuming there isn't any load folding for cmpps, and vector constants
-  // are not allowed in PNaCl.
+  // Assuming there isn't any load folding for cmpps, and vector constants are
+  // not allowed in PNaCl.
   assert(llvm::isa<Variable>(this->getSrc(1)));
   const auto SrcVar = llvm::cast<Variable>(this->getSrc(1));
   if (SrcVar->hasReg()) {
     Asm->cmpps(InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                    this->getDest()->getRegNum()),
                InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                    SrcVar->getRegNum()),
                Condition);
   } else {
     typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
@@ skipping 288 matching lines @@
                                                           ->getType()]
              .SdSsString << "\t";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Ucomiss<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
-  // Currently src0 is always a variable by convention, to avoid having
-  // two memory operands.
+  // Currently src0 is always a variable by convention, to avoid having two
+  // memory operands.
   assert(llvm::isa<Variable>(this->getSrc(0)));
   const auto Src0Var = llvm::cast<Variable>(this->getSrc(0));
   Type Ty = Src0Var->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::ucomiss,
                  &InstX86Base<Machine>::Traits::Assembler::ucomiss};
   emitIASRegOpTyXMM<Machine>(Func, Ty, Src0Var, this->getSrc(1), Emitter);
 }
 
 template <class Machine>
@@ skipping 281 matching lines @@
   if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
       isIntegerConstant(Src)) {
     Str << "\tmovabs\t";
   } else {
     Str << "\tmov"
         << (!isScalarFloatingType(DestTy)
                 ? this->getWidthString(SrcTy)
                 : InstX86Base<Machine>::Traits::TypeAttributes[DestTy]
                       .SdSsString) << "\t";
   }
-  // For an integer truncation operation, src is wider than dest.
-  // Ideally, we use a mov instruction whose data width matches the
-  // narrower dest.  This is a problem if e.g. src is a register like
-  // esi or si where there is no 8-bit version of the register.  To be
-  // safe, we instead widen the dest to match src.  This works even
-  // for stack-allocated dest variables because typeWidthOnStack()
-  // pads to a 4-byte boundary even if only a lower portion is used.
-  // TODO: This assert disallows usages such as copying a floating point
-  // value between a vector and a scalar (which movss is used for).
-  // Clean this up.
+  // For an integer truncation operation, src is wider than dest. Ideally, we
+  // use a mov instruction whose data width matches the narrower dest. This is
+  // a problem if e.g. src is a register like esi or si where there is no 8-bit
+  // version of the register. To be safe, we instead widen the dest to match
+  // src. This works even for stack-allocated dest variables because
+  // typeWidthOnStack() pads to a 4-byte boundary even if only a lower portion
+  // is used.
+  // TODO: This assert disallows usages such as copying a floating
+  // point value between a vector and a scalar (which movss is used for). Clean
+  // this up.
   assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
          Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
   Src->emit(Func);
   Str << ", ";
   this->getDest()->asType(SrcTy)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Mov<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   // Mov can be used for GPRs or XMM registers. Also, the type does not
-  // necessarily match (Mov can be used for bitcasts). However, when
-  // the type does not match, one of the operands must be a register.
-  // Thus, the strategy is to find out if Src or Dest are a register,
-  // then use that register's type to decide on which emitter set to use.
-  // The emitter set will include reg-reg movs, but that case should
-  // be unused when the types don't match.
+  // necessarily match (Mov can be used for bitcasts). However, when the type
+  // does not match, one of the operands must be a register. Thus, the strategy
+  // is to find out if Src or Dest are a register, then use that register's
+  // type to decide on which emitter set to use. The emitter set will include
+  // reg-reg movs, but that case should be unused when the types don't match.
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       XmmRegEmitter = {&InstX86Base<Machine>::Traits::Assembler::movss,
                        &InstX86Base<Machine>::Traits::Assembler::movss};
   static const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
       GPRRegEmitter = {&InstX86Base<Machine>::Traits::Assembler::mov,
                        &InstX86Base<Machine>::Traits::Assembler::mov,
                        &InstX86Base<Machine>::Traits::Assembler::mov};
   static const typename InstX86Base<
       Machine>::Traits::Assembler::GPREmitterAddrOp GPRAddrEmitter = {
       &InstX86Base<Machine>::Traits::Assembler::mov,
       &InstX86Base<Machine>::Traits::Assembler::mov};
-  // For an integer truncation operation, src is wider than dest.
-  // Ideally, we use a mov instruction whose data width matches the
-  // narrower dest.  This is a problem if e.g. src is a register like
-  // esi or si where there is no 8-bit version of the register.  To be
-  // safe, we instead widen the dest to match src.  This works even
-  // for stack-allocated dest variables because typeWidthOnStack()
-  // pads to a 4-byte boundary even if only a lower portion is used.
-  // TODO: This assert disallows usages such as copying a floating point
-  // value between a vector and a scalar (which movss is used for).
-  // Clean this up.
+  // For an integer truncation operation, src is wider than dest. Ideally, we
+  // use a mov instruction whose data width matches the narrower dest. This is
+  // a problem if e.g. src is a register like esi or si where there is no 8-bit
+  // version of the register. To be safe, we instead widen the dest to match
+  // src. This works even for stack-allocated dest variables because
+  // typeWidthOnStack() pads to a 4-byte boundary even if only a lower portion
+  // is used.
+  // TODO: This assert disallows usages such as copying a floating
+  // point value between a vector and a scalar (which movss is used for). Clean
+  // this up.
   assert(
       Func->getTarget()->typeWidthInBytesOnStack(this->getDest()->getType()) ==
       Func->getTarget()->typeWidthInBytesOnStack(Src->getType()));
   if (Dest->hasReg()) {
     if (isScalarFloatingType(DestTy)) {
       emitIASRegOpTyXMM<Machine>(Func, DestTy, Dest, Src, XmmRegEmitter);
       return;
     } else {
       assert(isScalarIntegerType(DestTy));
       // Widen DestTy for truncation (see above note). We should only do this
@@ skipping 12 matching lines @@
                      Value);
         return;
       }
       if (isScalarIntegerType(SrcTy)) {
         DestTy = SrcTy;
       }
       emitIASRegOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
-    // Dest must be Stack and Src *could* be a register. Use Src's type
-    // to decide on the emitters.
+    // Dest must be Stack and Src *could* be a register. Use Src's type to
+    // decide on the emitters.
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(Dest));
     if (isScalarFloatingType(SrcTy)) {
       // Src must be a register.
       const auto SrcVar = llvm::cast<Variable>(Src);
       assert(SrcVar->hasReg());
       typename InstX86Base<Machine>::Traits::Assembler *Asm =
           Func->getAssembler<
@@ skipping 12 matching lines @@
   }
 }
 
 template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const auto SrcVar = llvm::cast<Variable>(this->getSrc(0));
-  // For insert/extract element (one of Src/Dest is an Xmm vector and
-  // the other is an int type).
+  // For insert/extract element (one of Src/Dest is an Xmm vector and the other
+  // is an int type).
   if (SrcVar->getType() == IceType_i32 ||
       (InstX86Base<Machine>::Traits::Is64Bit &&
        SrcVar->getType() == IceType_i64)) {
     assert(isVectorType(Dest->getType()) ||
            (isScalarFloatingType(Dest->getType()) &&
             typeWidthInBytes(SrcVar->getType()) ==
                 typeWidthInBytes(Dest->getType())));
     assert(Dest->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
@@ skipping 33 matching lines @@
               ->stackVarToAsmOperand(Dest));
       Asm->movd(Dest->getType(), StackAddr, SrcReg);
     }
   }
 }
 
 template <class Machine>
 void InstX86Movp<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  // TODO(wala,stichnot): movups works with all vector operands, but
-  // there exist other instructions (movaps, movdqa, movdqu) that may
-  // perform better, depending on the data type and alignment of the
-  // operands.
+  // TODO(wala,stichnot): movups works with all vector operands, but there
+  // exist other instructions (movaps, movdqa, movdqu) that may perform better,
+  // depending on the data type and alignment of the operands.
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Str << "\tmovups\t";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Movp<Machine>::emitIAS(const Cfg *Func) const {
@@ skipping 33 matching lines @@
   static const typename InstX86Base<
       Machine>::Traits::Assembler::XmmEmitterMovOps Emitter = {
       &InstX86Base<Machine>::Traits::Assembler::movq,
       &InstX86Base<Machine>::Traits::Assembler::movq,
       &InstX86Base<Machine>::Traits::Assembler::movq};
   emitIASMovlikeXMM<Machine>(Func, Dest, Src, Emitter);
 }
 
 template <class Machine>
 void InstX86MovssRegs<Machine>::emitIAS(const Cfg *Func) const {
-  // This is Binop variant is only intended to be used for reg-reg moves
-  // where part of the Dest register is untouched.
+  // This is Binop variant is only intended to be used for reg-reg moves where
+  // part of the Dest register is untouched.
   assert(this->getSrcSize() == 2);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
   const auto SrcVar = llvm::cast<Variable>(this->getSrc(1));
   assert(Dest->hasReg() && SrcVar->hasReg());
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Asm->movss(IceType_f32,
              InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                  Dest->getRegNum()),
              InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                  SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86Movsx<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
-  // Dest must be a > 8-bit register, but Src can be 8-bit. In practice
-  // we just use the full register for Dest to avoid having an
-  // OperandSizeOverride prefix. It also allows us to only dispatch on SrcTy.
+  // Dest must be a > 8-bit register, but Src can be 8-bit. In practice we just
+  // use the full register for Dest to avoid having an OperandSizeOverride
+  // prefix. It also allows us to only dispatch on SrcTy.
   Type SrcTy = Src->getType();
   assert(typeWidthInBytes(Dest->getType()) > 1);
   assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
   emitIASRegOpTyGPR<Machine, false, true>(Func, SrcTy, Dest, Src,
                                           this->Emitter);
 }
 
 template <class Machine>
 void InstX86Movzx<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
@@ skipping 31 matching lines @@
 
 template <class Machine> void InstX86Fld<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Type Ty = this->getSrc(0)->getType();
   SizeT Width = typeWidthInBytes(Ty);
   const auto Var = llvm::dyn_cast<Variable>(this->getSrc(0));
   if (Var && Var->hasReg()) {
-    // This is a physical xmm register, so we need to spill it to a
-    // temporary stack slot.
+    // This is a physical xmm register, so we need to spill it to a temporary
+    // stack slot.
     Str << "\tsubl\t$" << Width << ", %esp"
         << "\n";
     Str << "\tmov"
         << InstX86Base<Machine>::Traits::TypeAttributes[Ty].SdSsString << "\t";
     Var->emit(Func);
     Str << ", (%esp)\n";
     Str << "\tfld" << this->getFldString(Ty) << "\t"
         << "(%esp)\n";
     Str << "\taddl\t$" << Width << ", %esp";
     return;
   }
   Str << "\tfld" << this->getFldString(Ty) << "\t";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Operand *Src = this->getSrc(0);
   Type Ty = Src->getType();
   if (const auto Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->hasReg()) {
-      // This is a physical xmm register, so we need to spill it to a
-      // temporary stack slot.
+      // This is a physical xmm register, so we need to spill it to a temporary
+      // stack slot.
       Immediate Width(typeWidthInBytes(Ty));
       Asm->sub(IceType_i32,
                InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
                Width);
       typename InstX86Base<Machine>::Traits::Address StackSlot =
           typename InstX86Base<Machine>::Traits::Address(
               InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, 0);
       Asm->movss(Ty, StackSlot,
                  InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                      Var->getRegNum()));
@@ skipping 28 matching lines @@
   this->dumpSources(Func);
 }
 
 template <class Machine>
 void InstX86Fstp<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 0);
   // TODO(jvoung,stichnot): Utilize this by setting Dest to nullptr to
-  // "partially" delete the fstp if the Dest is unused.
-  // Even if Dest is unused, the fstp should be kept for the SideEffects
-  // of popping the stack.
+  // "partially" delete the fstp if the Dest is unused. Even if Dest is unused,
+  // the fstp should be kept for the SideEffects of popping the stack.
   if (!this->getDest()) {
     Str << "\tfstp\tst(0)";
     return;
   }
   Type Ty = this->getDest()->getType();
   size_t Width = typeWidthInBytes(Ty);
   if (!this->getDest()->hasReg()) {
     Str << "\tfstp" << this->getFldString(Ty) << "\t";
     this->getDest()->emit(Func);
     return;
   }
-  // Dest is a physical (xmm) register, so st(0) needs to go through
-  // memory.  Hack this by creating a temporary stack slot, spilling
-  // st(0) there, loading it into the xmm register, and deallocating
-  // the stack slot.
+  // Dest is a physical (xmm) register, so st(0) needs to go through memory.
+  // Hack this by creating a temporary stack slot, spilling st(0) there,
+  // loading it into the xmm register, and deallocating the stack slot.
   Str << "\tsubl\t$" << Width << ", %esp\n";
   Str << "\tfstp" << this->getFldString(Ty) << "\t"
       << "(%esp)\n";
   Str << "\tmov" << InstX86Base<Machine>::Traits::TypeAttributes[Ty].SdSsString
       << "\t"
       << "(%esp), ";
   this->getDest()->emit(Func);
   Str << "\n";
   Str << "\taddl\t$" << Width << ", %esp";
 }
 
 template <class Machine>
 void InstX86Fstp<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 0);
   const Variable *Dest = this->getDest();
   // TODO(jvoung,stichnot): Utilize this by setting Dest to nullptr to
-  // "partially" delete the fstp if the Dest is unused.
-  // Even if Dest is unused, the fstp should be kept for the SideEffects
-  // of popping the stack.
+  // "partially" delete the fstp if the Dest is unused. Even if Dest is unused,
+  // the fstp should be kept for the SideEffects of popping the stack.
   if (!Dest) {
     Asm->fstp(InstX86Base<Machine>::Traits::RegisterSet::getEncodedSTReg(0));
     return;
   }
   Type Ty = Dest->getType();
   if (!Dest->hasReg()) {
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(Dest));
     Asm->fstp(Ty, StackAddr);
   } else {
-    // Dest is a physical (xmm) register, so st(0) needs to go through
-    // memory.  Hack this by creating a temporary stack slot, spilling
-    // st(0) there, loading it into the xmm register, and deallocating
-    // the stack slot.
+    // Dest is a physical (xmm) register, so st(0) needs to go through memory.
+    // Hack this by creating a temporary stack slot, spilling st(0) there,
+    // loading it into the xmm register, and deallocating the stack slot.
     Immediate Width(typeWidthInBytes(Ty));
     Asm->sub(IceType_i32,
              InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, Width);
     typename InstX86Base<Machine>::Traits::Address StackSlot =
         typename InstX86Base<Machine>::Traits::Address(
             InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, 0);
     Asm->fstp(Ty, StackSlot);
     Asm->movss(Ty, InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
                        Dest->getRegNum()),
                StackSlot);
@@ skipping 49 matching lines @@
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<Machine>::Traits::TypeAttributes[this->getSrc(0)
                                                           ->getType()]
              .PackString << "\t";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = this->getDest();
-  // pextrw must take a register dest. There is an SSE4.1 version that takes
-  // a memory dest, but we aren't using it. For uniformity, just restrict
-  // them all to have a register dest for now.
+  // pextrw must take a register dest. There is an SSE4.1 version that takes a
+  // memory dest, but we aren't using it. For uniformity, just restrict them
+  // all to have a register dest for now.
   assert(Dest->hasReg());
   Dest->asType(IceType_i32)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = this->getDest();
   Type DispatchTy = Dest->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
-  // pextrw must take a register dest. There is an SSE4.1 version that takes
-  // a memory dest, but we aren't using it. For uniformity, just restrict
-  // them all to have a register dest for now.
+  // pextrw must take a register dest. There is an SSE4.1 version that takes a
+  // memory dest, but we aren't using it. For uniformity, just restrict them
+  // all to have a register dest for now.
   assert(Dest->hasReg());
   // pextrw's Src(0) must be a register (both SSE4.1 and SSE2).
   assert(llvm::cast<Variable>(this->getSrc(0))->hasReg());
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pextr, nullptr};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
@@ skipping 40 matching lines @@
 void InstX86Pinsr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = this->getSrc(1);
   Type DispatchTy = Src0->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
-  // If src1 is a register, it should always be r32 (this should fall out
-  // from the encodings for ByteRegs overlapping the encodings for r32),
-  // but we have to trust the regalloc to not choose "ah", where it
-  // doesn't overlap.
+  // If src1 is a register, it should always be r32 (this should fall out from
+  // the encodings for ByteRegs overlapping the encodings for r32), but we have
+  // to trust the regalloc to not choose "ah", where it doesn't overlap.
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pinsr,
                      &InstX86Base<Machine>::Traits::Assembler::pinsr};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
@@ skipping 394 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H