| OLD | NEW |
| 1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// | 1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 88 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 99 } | 99 } |
| 100 | 100 |
| 101 void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const { | 101 void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const { |
| 102 if (!BuildDefs::dump()) | 102 if (!BuildDefs::dump()) |
| 103 return; | 103 return; |
| 104 Ostream &Str = Func->getContext()->getStrEmit(); | 104 Ostream &Str = Func->getContext()->getStrEmit(); |
| 105 if (SegmentReg != DefaultSegment) { | 105 if (SegmentReg != DefaultSegment) { |
| 106 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); | 106 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); |
| 107 Str << "%" << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; | 107 Str << "%" << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; |
| 108 } | 108 } |
| 109 // Emit as Offset(Base,Index,1<<Shift). | 109 // Emit as Offset(Base,Index,1<<Shift). Offset is emitted without the leading |
| 110 // Offset is emitted without the leading '$'. | 110 // '$'. Omit the (Base,Index,1<<Shift) part if Base==nullptr. |
| 111 // Omit the (Base,Index,1<<Shift) part if Base==nullptr. | |
| 112 if (!Offset) { | 111 if (!Offset) { |
| 113 // No offset, emit nothing. | 112 // No offset, emit nothing. |
| 114 } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) { | 113 } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) { |
| 115 if (Base == nullptr || CI->getValue()) | 114 if (Base == nullptr || CI->getValue()) |
| 116 // Emit a non-zero offset without a leading '$'. | 115 // Emit a non-zero offset without a leading '$'. |
| 117 Str << CI->getValue(); | 116 Str << CI->getValue(); |
| 118 } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) { | 117 } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) { |
| 119 CR->emitWithoutPrefix(Func->getTarget()); | 118 CR->emitWithoutPrefix(Func->getTarget()); |
| 120 } else { | 119 } else { |
| 121 llvm_unreachable("Invalid offset type for x86 mem operand"); | 120 llvm_unreachable("Invalid offset type for x86 mem operand"); |
| (...skipping 152 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 274 Var->dump(Func); | 273 Var->dump(Func); |
| 275 else | 274 else |
| 276 Var->dump(Str); | 275 Var->dump(Str); |
| 277 Str << ")"; | 276 Str << ")"; |
| 278 } | 277 } |
| 279 | 278 |
| 280 } // namespace X86Internal | 279 } // namespace X86Internal |
| 281 } // end of namespace Ice | 280 } // end of namespace Ice |
| 282 | 281 |
| 283 X86INSTS_DEFINE_STATIC_DATA(TargetX8632) | 282 X86INSTS_DEFINE_STATIC_DATA(TargetX8632) |
| OLD | NEW |