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src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF
 #define SUBZERO_SRC_ICEINSTARM32_DEF
 
 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
 //
 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always.
-// TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off
-// (native mode).
+// TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off (native
+// mode).
 //
 // IP is not considered isInt to reserve it as a scratch register. A scratch
 // register is useful for expanding instructions post-register allocation.
 //
-// LR is not considered isInt to avoid being allocated as a register.
-// It is technically preserved, but save/restore is handled separately,
-// based on whether or not the function MaybeLeafFunc.
+// LR is not considered isInt to avoid being allocated as a register. It is
+// technically preserved, but save/restore is handled separately, based on
+// whether or not the function MaybeLeafFunc.
 
 // ALIASESn is a family of macros that we use to define register aliasing in
 // ARM32. n indicates how many aliases are being provided to the macro. It
-// assumes the parameters are register names declared in a namespace/class named
-// RegARM32.
+// assumes the parameters are register names declared in a namespace/class
+// named RegARM32.
 #define ALIASES1(r0)                                                           \
     {RegARM32::r0}
 #define ALIASES2(r0, r1)                                                       \
     {RegARM32::r0, RegARM32::r1}
 #define ALIASES3(r0, r1, r2)                                                   \
     {RegARM32::r0, RegARM32::r1, RegARM32::r2}
 #define ALIASES4(r0, r1, r2, r3)                                               \
     {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3}
 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6)                                   \
     {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4,     \
@@ skipping 101 matching lines @@
     ALIASES3(Reg_s28, Reg_d14, Reg_q7))                                        \
   X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0,                                \
     ALIASES3(Reg_s29, Reg_d14, Reg_q7))                                        \
   X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0,                                \
     ALIASES3(Reg_s30, Reg_d15, Reg_q7))                                        \
   X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0,                                \
     ALIASES3(Reg_s31, Reg_d15, Reg_q7)) 
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isFP32,isFP64, isVec128, aliases_init)
 
-// D registers 0-7 are scratch, 8-15 are preserved, and 16-31
-// are also scratch (if supported by the D32 feature vs D16).
-// D registers are defined in reverse order so that, during register allocation,
-// Subzero will prefer higher D registers. In processors supporting the D32
-// feature this will effectively cause double allocation to bias towards
-// allocating "high" D registers, which do not alias any S registers.
+// D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
+// (if supported by the D32 feature vs D16). D registers are defined in reverse
+// order so that, during register allocation, Subzero will prefer higher D
+// registers. In processors supporting the D32 feature this will effectively
+// cause double allocation to bias towards allocating "high" D registers, which
+// do not alias any S registers.
 //
 // Regenerate this with the following python script:
 // def print_dregs():
 //   for i in xrange(31, 15, -1):
 //     is_scratch = 1 if (i < 8 or i >= 16) else 0
 //     is_preserved = 1 if (8 <= i and i < 16) else 0
 //     print ('  X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
 //            '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' +
 //            'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2})    \\').format(
 //            regnum=i, regnum_q=i>>1, scratch=is_scratch,
@@ skipping 73 matching lines @@
     ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1))                               \
   X(Reg_d2 , 2 ,  "d2", 1, 0, 0, 0, 0, 0, 1, 0,                                \
     ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1))                               \
   X(Reg_d1 , 1 ,  "d1", 1, 0, 0, 0, 0, 0, 1, 0,                                \
     ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0))                               \
   X(Reg_d0 , 0 ,  "d0", 1, 0, 0, 0, 0, 0, 1, 0,                                \
     ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0)) 
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isFP32, isFP64, isVec128, aliases_init)
 
-// Q registers 0-3 are scratch, 4-7 are preserved, and 8-15
-// are also scratch (if supported by the D32 feature).
-// Q registers are defined in reverse order for the same reason as D registers.
+// Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
+// (if supported by the D32 feature). Q registers are defined in reverse order
+// for the same reason as D registers.
 //
 // Regenerate this with the following python script:
 // def print_qregs():
 //   for i in xrange(15, 7, -1):
 //     is_scratch = 1 if (i < 4 or i >= 8) else 0
 //     is_preserved = 1 if (4 <= i and i < 8) else 0
 //     print ('  X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
 //            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' +
 //            'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
 //            'Reg_q{regnum:<2}))    \\').format(
@@ skipping 46 matching lines @@
   X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 1,                                 \
     ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2))    \
   X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 1,                                 \
     ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1))    \
   X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 1,                                 \
     ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0)) 
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isFP32, isFP64, isVec128, alias_init)
 #undef ALIASES
 
-// We also provide a combined table, so that there is a namespace where
-// all of the registers are considered and have distinct numberings.
-// This is in contrast to the above, where the "encode" is based on how
-// the register numbers will be encoded in binaries and values can overlap.
+// We also provide a combined table, so that there is a namespace where all of
+// the registers are considered and have distinct numberings. This is in
+// contrast to the above, where the "encode" is based on how the register
+// numbers will be encoded in binaries and values can overlap.
 #define REGARM32_TABLE                                                         \
   /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt,         \
      isFP32, isFP64, isVec128, alias_init */                                   \
   REGARM32_GPR_TABLE                                                           \
   REGARM32_FP32_TABLE                                                          \
   REGARM32_FP64_TABLE                                                          \
   REGARM32_VEC128_TABLE
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isFP32, isFP64, isVec128, alias_init)
 
 #define REGARM32_TABLE_BOUNDS                                                  \
   /* val, init */                                                              \
   X(Reg_GPR_First, = Reg_r0)                                                   \
   X(Reg_GPR_Last, = Reg_pc)                                                    \
   X(Reg_SREG_First, = Reg_s0)                                                  \
   X(Reg_SREG_Last, = Reg_s31)                                                  \
   X(Reg_DREG_First, = Reg_d0)                                                  \
   X(Reg_DREG_Last, = Reg_d31)                                                  \
   X(Reg_QREG_First, = Reg_q0)                                                  \
   X(Reg_QREG_Last, = Reg_q15)
 // define X(val, init)
 
 // Load/Store instruction width suffixes and FP/Vector element size suffixes
-// the # of offset bits allowed as part of an addressing mode (for sign or
-// zero extending load/stores).
+// the # of offset bits allowed as part of an addressing mode (for sign or zero
+// extending load/stores).
 #define ICETYPEARM32_TABLE                                                     \
   /* tag,          element type, int_width, vec_width, addr bits sext, zext */ \
   X(IceType_void,  IceType_void, "" , ""    , 0 , 0)                           \
   X(IceType_i1,    IceType_void, "b", ""    , 8 , 12)                          \
   X(IceType_i8,    IceType_void, "b", ""    , 8 , 12)                          \
   X(IceType_i16,   IceType_void, "h", ""    , 8 , 8)                           \
   X(IceType_i32,   IceType_void, "" , ""    , 12, 12)                          \
   X(IceType_i64,   IceType_void, "d", ""    , 8 , 8)                           \
   X(IceType_f32,   IceType_void, "" , ".f32", 10, 10)                          \
   X(IceType_f64,   IceType_void, "" , ".f64", 10, 10)                          \
   X(IceType_v4i1,  IceType_i32 , "" , ".i32", 0 , 0)                           \
   X(IceType_v8i1,  IceType_i16 , "" , ".i16", 0 , 0)                           \
   X(IceType_v16i1, IceType_i8  , "" , ".i8" , 0 , 0)                           \
   X(IceType_v16i8, IceType_i8  , "" , ".i8" , 0 , 0)                           \
   X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0)                           \
   X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0)                           \
   X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0)
 //#define X(tag, elementty, int_width, vec_width, sbits, ubits)
 
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 #define ICEINSTARM32SHIFT_TABLE                                                \
   /* enum value, emit */                                                       \
   X(LSL, "lsl")                                                                \
   X(LSR, "lsr")                                                                \
   X(ASR, "asr")                                                                \
   X(ROR, "ror")                                                                \
   X(RRX, "rrx")
 //#define X(tag, emit)
 
-// Attributes for the condition code 4-bit encoding (that is independent
-// of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
-// Z = 1, and NE is 1, but corresponds to Z = 0.
+// Attributes for the condition code 4-bit encoding (that is independent of the
+// APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE
+// is 1, but corresponds to Z = 0.
 #define ICEINSTARM32COND_TABLE                                                 \
   /* enum value, encoding, opposite, emit */                                   \
   X(EQ, 0 , NE, "eq")   /* equal */                                            \
   X(NE, 1 , EQ, "ne")   /* not equal */                                        \
   X(CS, 2 , CC, "cs")   /* carry set/unsigned (AKA hs: higher or same) */      \
   X(CC, 3 , CS, "cc")   /* carry clear/unsigned (AKA lo: lower) */             \
   X(MI, 4 , PL, "mi")   /* minus/negative */                                   \
   X(PL, 5 , MI, "pl")   /* plus/positive or zero */                            \
   X(VS, 6 , VC, "vs")   /* overflow (float unordered) */                       \
   X(VC, 7 , VS, "vc")   /* no overflow (float not unordered) */                \
   X(HI, 8 , LS, "hi")   /* unsigned higher */                                  \
   X(LS, 9 , HI, "ls")   /* unsigned lower or same */                           \
   X(GE, 10, LT, "ge")  /* signed greater than or equal */                      \
   X(LT, 11, GE, "lt")  /* signed less than */                                  \
   X(GT, 12, LE, "gt")  /* signed greater than */                               \
   X(LE, 13, GT, "le")  /* signed less than or equal */                         \
   X(AL, 14, kNone, "") /* always (unconditional) */                            \
   X(kNone, 15, kNone, "??") /* special condition / none */
 //#define(tag, encode, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF