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src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// This file implements the InstARM32 and OperandARM32 classes,
-/// primarily the constructors and the dump()/emit() methods.
+/// This file implements the InstARM32 and OperandARM32 classes, primarily the
+/// constructors and the dump()/emit() methods.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceInstARM32.h"
 
 #include "IceAssemblerARM32.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceInst.h"
 #include "IceOperand.h"
@@ skipping 241 matching lines @@
   addSource(SrcAmount);
 }
 
 InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue,
                          const CfgNode *TargetFalse,
                          const InstARM32Label *Label, CondARM32::Cond Pred)
     : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred),
       TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {}
 
 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) {
-  // If there is no next block, then there can be no fallthrough to
-  // optimize.
+  // If there is no next block, then there can be no fallthrough to optimize.
   if (NextNode == nullptr)
     return false;
   // Intra-block conditional branches can't be optimized.
   if (Label)
     return false;
-  // If there is no fallthrough node, such as a non-default case label
-  // for a switch instruction, then there is no opportunity to
-  // optimize.
+  // If there is no fallthrough node, such as a non-default case label for a
+  // switch instruction, then there is no opportunity to optimize.
   if (getTargetFalse() == nullptr)
     return false;
 
   // Unconditional branch to the next node can be removed.
   if (isUnconditionalBranch() && getTargetFalse() == NextNode) {
     assert(getTargetTrue() == nullptr);
     setDeleted();
     return true;
   }
-  // If the fallthrough is to the next node, set fallthrough to nullptr
-  // to indicate.
+  // If the fallthrough is to the next node, set fallthrough to nullptr to
+  // indicate.
   if (getTargetFalse() == NextNode) {
     TargetFalse = nullptr;
     return true;
   }
-  // If TargetTrue is the next node, and TargetFalse is not nullptr
-  // (which was already tested above), then invert the branch
-  // condition, swap the targets, and set new fallthrough to nullptr.
+  // If TargetTrue is the next node, and TargetFalse is not nullptr (which was
+  // already tested above), then invert the branch condition, swap the targets,
+  // and set new fallthrough to nullptr.
   if (getTargetTrue() == NextNode) {
     assert(Predicate != CondARM32::AL);
     setPredicate(getOppositeCondition(getPredicate()));
     TargetTrue = getTargetFalse();
     TargetFalse = nullptr;
     return true;
   }
   return false;
 }
 
@@ skipping 19 matching lines @@
 InstARM32Label::InstARM32Label(Cfg *Func, TargetARM32 *Target)
     : InstARM32(Func, InstARM32::Label, 0, nullptr),
       Number(Target->makeNextLabelNumber()) {}
 
 IceString InstARM32Label::getName(const Cfg *Func) const {
   return ".L" + Func->getFunctionName() + "$local$__" + std::to_string(Number);
 }
 
 InstARM32Pop::InstARM32Pop(Cfg *Func, const VarList &Dests)
     : InstARM32(Func, InstARM32::Pop, 0, nullptr), Dests(Dests) {
-  // Track modifications to Dests separately via FakeDefs.
-  // Also, a pop instruction affects the stack pointer and so it should not
-  // be allowed to be automatically dead-code eliminated. This is automatic
-  // since we leave the Dest as nullptr.
+  // Track modifications to Dests separately via FakeDefs. Also, a pop
+  // instruction affects the stack pointer and so it should not be allowed to
+  // be automatically dead-code eliminated. This is automatic since we leave
+  // the Dest as nullptr.
 }
 
 InstARM32Push::InstARM32Push(Cfg *Func, const VarList &Srcs)
     : InstARM32(Func, InstARM32::Push, Srcs.size(), nullptr) {
   for (Variable *Source : Srcs)
     addSource(Source);
 }
 
 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source)
     : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) {
@@ skipping 88 matching lines @@
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Variable *Dest = getDest();
   if (Dest->hasReg()) {
     IceString ActualOpcode = Opcode;
     Operand *Src0 = getSrc(0);
     if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) {
       if (!Src0V->hasReg()) {
-        // Always use the whole stack slot. A 32-bit load has a larger range
-        // of offsets than 16-bit, etc.
+        // Always use the whole stack slot. A 32-bit load has a larger range of
+        // offsets than 16-bit, etc.
         ActualOpcode = IceString("ldr");
       }
     } else {
       if (llvm::isa<OperandARM32Mem>(Src0))
         ActualOpcode = IceString("ldr") + getWidthString(Dest->getType());
     }
     Str << "\t" << ActualOpcode << getPredicate() << "\t";
     getDest()->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
@@ skipping 190 matching lines @@
     }
   }
 }
 
 void InstARM32Call::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   if (llvm::isa<ConstantInteger32>(getCallTarget())) {
-    // This shouldn't happen (typically have to copy the full 32-bits
-    // to a register and do an indirect jump).
+    // This shouldn't happen (typically have to copy the full 32-bits to a
+    // register and do an indirect jump).
     llvm::report_fatal_error("ARM32Call to ConstantInteger32");
   } else if (const auto CallTarget =
                  llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
-    // Calls only have 24-bits, but the linker should insert veneers to
-    // extend the range if needed.
+    // Calls only have 24-bits, but the linker should insert veneers to extend
+    // the range if needed.
     Str << "\t"
         << "bl"
         << "\t";
     CallTarget->emitWithoutPrefix(Func->getTarget());
   } else {
     Str << "\t"
         << "blx"
         << "\t";
     getCallTarget()->emit(Func);
   }
@@ skipping 469 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice