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src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// This file implements the TargetLoweringX86Base class, which
-/// consists almost entirely of the lowering sequence for each
-/// high-level instruction.
+/// This file implements the TargetLoweringX86Base class, which consists almost
+/// entirely of the lowering sequence for each high-level instruction.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceDefs.h"
@@ skipping 32 matching lines @@
 
 public:
   BoolFoldingEntry() = default;
   explicit BoolFoldingEntry(Inst *I);
   BoolFoldingEntry &operator=(const BoolFoldingEntry &) = default;
   /// Instr is the instruction producing the i1-type variable of interest.
   Inst *Instr = nullptr;
   /// IsComplex is the cached result of BoolFolding::hasComplexLowering(Instr).
   bool IsComplex = false;
   /// IsLiveOut is initialized conservatively to true, and is set to false when
-  /// we encounter an instruction that ends Var's live range.  We disable the
-  /// folding optimization when Var is live beyond this basic block.  Note that
+  /// we encounter an instruction that ends Var's live range. We disable the
+  /// folding optimization when Var is live beyond this basic block. Note that
   /// if liveness analysis is not performed (e.g. in Om1 mode), IsLiveOut will
   /// always be true and the folding optimization will never be performed.
   bool IsLiveOut = true;
   // NumUses counts the number of times Var is used as a source operand in the
-  // basic block.  If IsComplex is true and there is more than one use of Var,
+  // basic block. If IsComplex is true and there is more than one use of Var,
   // then the folding optimization is disabled for Var.
   uint32_t NumUses = 0;
 };
 
 template <class MachineTraits> class BoolFolding {
 public:
   enum BoolFoldingProducerKind {
     PK_None,
     // TODO(jpp): PK_Icmp32 is no longer meaningful. Rename to PK_IcmpNative.
     PK_Icmp32,
@@ skipping 76 matching lines @@
     case InstCast::Zext:
       return CK_Zext;
     }
   }
   return CK_None;
 }
 
 /// Returns true if the producing instruction has a "complex" lowering sequence.
 /// This generally means that its lowering sequence requires more than one
 /// conditional branch, namely 64-bit integer compares and some floating-point
-/// compares.  When this is true, and there is more than one consumer, we prefer
+/// compares. When this is true, and there is more than one consumer, we prefer
 /// to disable the folding optimization because it minimizes branches.
 template <class MachineTraits>
 bool BoolFolding<MachineTraits>::hasComplexLowering(const Inst *Instr) {
   switch (getProducerKind(Instr)) {
   default:
     return false;
   case PK_Icmp64:
     return true;
   case PK_Fcmp:
     return MachineTraits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()]
@@ skipping 35 matching lines @@
   }
   for (auto &I : Producers) {
     // Ignore entries previously marked invalid.
     if (I.second.Instr == nullptr)
       continue;
     // Disable the producer if its dest may be live beyond this block.
     if (I.second.IsLiveOut) {
       setInvalid(I.first);
       continue;
     }
-    // Mark as "dead" rather than outright deleting.  This is so that other
+    // Mark as "dead" rather than outright deleting. This is so that other
     // peephole style optimizations during or before lowering have access to
-    // this instruction in undeleted form.  See for example
+    // this instruction in undeleted form. See for example
     // tryOptimizedCmpxchgCmpBr().
     I.second.Instr->setDead();
   }
 }
 
 template <class MachineTraits>
 const Inst *
 BoolFolding<MachineTraits>::getProducerFor(const Operand *Opnd) const {
   auto *Var = llvm::dyn_cast<const Variable>(Opnd);
   if (Var == nullptr)
@@ skipping 58 matching lines @@
     if (Func->hasError())
       return;
     Func->deletePhis();
     if (Func->hasError())
       return;
     Func->dump("After Phi lowering");
   }
 
   // Run this early so it can be used to focus optimizations on potentially hot
   // code.
-  // TODO(stichnot,ascull): currently only used for regalloc not expensive high
-  // level optimizations which could be focused on potentially hot code.
+  // TODO(stichnot,ascull): currently only used for regalloc not
+  // expensive high level optimizations which could be focused on potentially
+  // hot code.
   Func->computeLoopNestDepth();
   Func->dump("After loop nest depth analysis");
 
   // Address mode optimization.
   Func->getVMetadata()->init(VMK_SingleDefs);
   Func->doAddressOpt();
 
-  // Find read-modify-write opportunities.  Do this after address mode
+  // Find read-modify-write opportunities. Do this after address mode
   // optimization so that doAddressOpt() doesn't need to be applied to RMW
   // instructions as well.
   findRMW();
   Func->dump("After RMW transform");
 
   // Argument lowering
   Func->doArgLowering();
 
-  // Target lowering.  This requires liveness analysis for some parts of the
-  // lowering decisions, such as compare/branch fusing.  If non-lightweight
+  // Target lowering. This requires liveness analysis for some parts of the
+  // lowering decisions, such as compare/branch fusing. If non-lightweight
   // liveness analysis is used, the instructions need to be renumbered first
   // TODO: This renumbering should only be necessary if we're actually
   // calculating live intervals, which we only do for register allocation.
   Func->renumberInstructions();
   if (Func->hasError())
     return;
 
-  // TODO: It should be sufficient to use the fastest liveness calculation, i.e.
-  // livenessLightweight().  However, for some reason that slows down the rest
-  // of the translation.  Investigate.
+  // TODO: It should be sufficient to use the fastest liveness calculation,
+  // i.e. livenessLightweight(). However, for some reason that slows down the
+  // rest of the translation. Investigate.
   Func->liveness(Liveness_Basic);
   if (Func->hasError())
     return;
   Func->dump("After x86 address mode opt");
 
   // Disable constant blinding or pooling for load optimization.
   {
     BoolFlagSaver B(RandomizationPoolingPaused, true);
     doLoadOpt();
   }
   Func->genCode();
   if (Func->hasError())
     return;
   Func->dump("After x86 codegen");
 
   // Register allocation. This requires instruction renumbering and full
   // liveness analysis. Loops must be identified before liveness so variable
   // use weights are correct.
   Func->renumberInstructions();
   if (Func->hasError())
     return;
   Func->liveness(Liveness_Intervals);
   if (Func->hasError())
     return;
-  // Validate the live range computations.  The expensive validation call is
+  // Validate the live range computations. The expensive validation call is
   // deliberately only made when assertions are enabled.
   assert(Func->validateLiveness());
   // The post-codegen dump is done here, after liveness analysis and associated
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial x8632 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
   Func->dump("After linear scan regalloc");
 
   if (Ctx->getFlags().getPhiEdgeSplit()) {
     Func->advancedPhiLowering();
     Func->dump("After advanced Phi lowering");
   }
 
   // Stack frame mapping.
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   Func->contractEmptyNodes();
   Func->reorderNodes();
 
   // Shuffle basic block order if -reorder-basic-blocks is enabled.
   Func->shuffleNodes();
 
-  // Branch optimization.  This needs to be done just before code emission.  In
+  // Branch optimization.  This needs to be done just before code emission. In
   // particular, no transformations that insert or reorder CfgNodes should be
-  // done after branch optimization.  We go ahead and do it before nop insertion
+  // done after branch optimization. We go ahead and do it before nop insertion
   // to reduce the amount of work needed for searching for opportunities.
   Func->doBranchOpt();
   Func->dump("After branch optimization");
 
   // Nop insertion if -nop-insertion is enabled.
   Func->doNopInsertion();
 
   // Mark nodes that require sandbox alignment
   if (Ctx->getFlags().getUseSandboxing())
     Func->markNodesForSandboxing();
@@ skipping 86 matching lines @@
   }
   return false;
 }
 
 template <class Machine> void TargetX86Base<Machine>::findRMW() {
   Func->dump("Before RMW");
   OstreamLocker L(Func->getContext());
   Ostream &Str = Func->getContext()->getStrDump();
   for (CfgNode *Node : Func->getNodes()) {
     // Walk through the instructions, considering each sequence of 3
-    // instructions, and look for the particular RMW pattern.  Note that this
-    // search can be "broken" (false negatives) if there are intervening deleted
-    // instructions, or intervening instructions that could be safely moved out
-    // of the way to reveal an RMW pattern.
+    // instructions, and look for the particular RMW pattern. Note that this
+    // search can be "broken" (false negatives) if there are intervening
+    // deleted instructions, or intervening instructions that could be safely
+    // moved out of the way to reveal an RMW pattern.
     auto E = Node->getInsts().end();
     auto I1 = E, I2 = E, I3 = Node->getInsts().begin();
     for (; I3 != E; I1 = I2, I2 = I3, ++I3) {
       // Make I3 skip over deleted instructions.
       while (I3 != E && I3->isDeleted())
         ++I3;
       if (I1 == E || I2 == E || I3 == E)
         continue;
       assert(!I1->isDeleted());
       assert(!I2->isDeleted());
       assert(!I3->isDeleted());
       if (auto *Load = llvm::dyn_cast<InstLoad>(I1)) {
         if (auto *Arith = llvm::dyn_cast<InstArithmetic>(I2)) {
           if (auto *Store = llvm::dyn_cast<InstStore>(I3)) {
             // Look for:
             //   a = Load addr
             //   b = <op> a, other
             //   Store b, addr
             // Change to:
             //   a = Load addr
             //   b = <op> a, other
             //   x = FakeDef
             //   RMW <op>, addr, other, x
             //   b = Store b, addr, x
             // Note that inferTwoAddress() makes sure setDestNonKillable() gets
             // called on the updated Store instruction, to avoid liveness
             // problems later.
             //
             // With this transformation, the Store instruction acquires a Dest
-            // variable and is now subject to dead code elimination if there are
-            // no more uses of "b".  Variable "x" is a beacon for determining
-            // whether the Store instruction gets dead-code eliminated.  If the
-            // Store instruction is eliminated, then it must be the case that
-            // the RMW instruction ends x's live range, and therefore the RMW
-            // instruction will be retained and later lowered.  On the other
-            // hand, if the RMW instruction does not end x's live range, then
-            // the Store instruction must still be present, and therefore the
-            // RMW instruction is ignored during lowering because it is
-            // redundant with the Store instruction.
+            // variable and is now subject to dead code elimination if there
+            // are no more uses of "b".  Variable "x" is a beacon for
+            // determining whether the Store instruction gets dead-code
+            // eliminated.  If the Store instruction is eliminated, then it
+            // must be the case that the RMW instruction ends x's live range,
+            // and therefore the RMW instruction will be retained and later
+            // lowered.  On the other hand, if the RMW instruction does not end
+            // x's live range, then the Store instruction must still be
+            // present, and therefore the RMW instruction is ignored during
+            // lowering because it is redundant with the Store instruction.
             //
             // Note that if "a" has further uses, the RMW transformation may
             // still trigger, resulting in two loads and one store, which is
-            // worse than the original one load and one store.  However, this is
-            // probably rare, and caching probably keeps it just as fast.
+            // worse than the original one load and one store.  However, this
+            // is probably rare, and caching probably keeps it just as fast.
             if (!isSameMemAddressOperand<Machine>(Load->getSourceAddress(),
                                                   Store->getAddr()))
               continue;
             Operand *ArithSrcFromLoad = Arith->getSrc(0);
             Operand *ArithSrcOther = Arith->getSrc(1);
             if (ArithSrcFromLoad != Load->getDest()) {
               if (!Arith->isCommutative() || ArithSrcOther != Load->getDest())
                 continue;
               std::swap(ArithSrcFromLoad, ArithSrcOther);
             }
@@ skipping 26 matching lines @@
 }
 
 // Converts a ConstantInteger32 operand into its constant value, or
 // MemoryOrderInvalid if the operand is not a ConstantInteger32.
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 
-/// Determines whether the dest of a Load instruction can be folded
-/// into one of the src operands of a 2-operand instruction.  This is
-/// true as long as the load dest matches exactly one of the binary
-/// instruction's src operands.  Replaces Src0 or Src1 with LoadSrc if
-/// the answer is true.
+/// Determines whether the dest of a Load instruction can be folded into one of
+/// the src operands of a 2-operand instruction. This is true as long as the
+/// load dest matches exactly one of the binary instruction's src operands.
+/// Replaces Src0 or Src1 with LoadSrc if the answer is true.
 inline bool canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest,
                                       Operand *&Src0, Operand *&Src1) {
   if (Src0 == LoadDest && Src1 != LoadDest) {
     Src0 = LoadSrc;
     return true;
   }
   if (Src0 != LoadDest && Src1 == LoadDest) {
     Src1 = LoadSrc;
     return true;
   }
   return false;
 }
 
 template <class Machine> void TargetX86Base<Machine>::doLoadOpt() {
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       Variable *LoadDest = nullptr;
       Operand *LoadSrc = nullptr;
       Inst *CurInst = Context.getCur();
       Inst *Next = Context.getNextInst();
-      // Determine whether the current instruction is a Load
-      // instruction or equivalent.
+      // Determine whether the current instruction is a Load instruction or
+      // equivalent.
       if (auto *Load = llvm::dyn_cast<InstLoad>(CurInst)) {
         // An InstLoad always qualifies.
         LoadDest = Load->getDest();
         const bool DoLegalize = false;
         LoadSrc = formMemoryOperand(Load->getSourceAddress(),
                                     LoadDest->getType(), DoLegalize);
       } else if (auto *Intrin = llvm::dyn_cast<InstIntrinsicCall>(CurInst)) {
-        // An AtomicLoad intrinsic qualifies as long as it has a valid
-        // memory ordering, and can be implemented in a single
-        // instruction (i.e., not i64 on x86-32).
+        // An AtomicLoad intrinsic qualifies as long as it has a valid memory
+        // ordering, and can be implemented in a single instruction (i.e., not
+        // i64 on x86-32).
         Intrinsics::IntrinsicID ID = Intrin->getIntrinsicInfo().ID;
         if (ID == Intrinsics::AtomicLoad &&
             (Traits::Is64Bit || Intrin->getDest()->getType() != IceType_i64) &&
             Intrinsics::isMemoryOrderValid(
                 ID, getConstantMemoryOrder(Intrin->getArg(1)))) {
           LoadDest = Intrin->getDest();
           const bool DoLegalize = false;
           LoadSrc = formMemoryOperand(Intrin->getArg(0), LoadDest->getType(),
                                       DoLegalize);
         }
       }
-      // A Load instruction can be folded into the following
-      // instruction only if the following instruction ends the Load's
-      // Dest variable's live range.
+      // A Load instruction can be folded into the following instruction only
+      // if the following instruction ends the Load's Dest variable's live
+      // range.
       if (LoadDest && Next && Next->isLastUse(LoadDest)) {
         assert(LoadSrc);
         Inst *NewInst = nullptr;
         if (auto *Arith = llvm::dyn_cast<InstArithmetic>(Next)) {
           Operand *Src0 = Arith->getSrc(0);
           Operand *Src1 = Arith->getSrc(1);
           if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
             NewInst = InstArithmetic::create(Func, Arith->getOp(),
                                              Arith->getDest(), Src0, Src1);
           }
@@ skipping 12 matching lines @@
                                        Fcmp->getDest(), Src0, Src1);
           }
         } else if (auto *Select = llvm::dyn_cast<InstSelect>(Next)) {
           Operand *Src0 = Select->getTrueOperand();
           Operand *Src1 = Select->getFalseOperand();
           if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
             NewInst = InstSelect::create(Func, Select->getDest(),
                                          Select->getCondition(), Src0, Src1);
           }
         } else if (auto *Cast = llvm::dyn_cast<InstCast>(Next)) {
-          // The load dest can always be folded into a Cast
-          // instruction.
+          // The load dest can always be folded into a Cast instruction.
           Variable *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0));
           if (Src0 == LoadDest) {
             NewInst = InstCast::create(Func, Cast->getCastKind(),
                                        Cast->getDest(), LoadSrc);
           }
         }
         if (NewInst) {
           CurInst->setDeleted();
           Next->setDeleted();
           Context.insert(NewInst);
-          // Update NewInst->LiveRangesEnded so that target lowering
-          // may benefit.  Also update NewInst->HasSideEffects.
+          // Update NewInst->LiveRangesEnded so that target lowering may
+          // benefit. Also update NewInst->HasSideEffects.
           NewInst->spliceLivenessInfo(Next, CurInst);
         }
       }
       Context.advanceCur();
       Context.advanceNext();
     }
   }
   Func->dump("After load optimization");
 }
 
@@ skipping 14 matching lines @@
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
-    // Specially mark esp as an "argument" so that it is considered
-    // live upon function entry.
+    // Specially mark esp as an "argument" so that it is considered live upon
+    // function entry.
     if (RegNum == Traits::RegisterSet::Reg_esp) {
       Func->addImplicitArg(Reg);
       Reg->setIgnoreLiveness();
     }
   }
   return Reg;
 }
 
 template <class Machine>
 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
@@ skipping 39 matching lines @@
     BaseRegNum = getFrameOrStackReg();
     if (!hasFramePointer())
       Offset += getStackAdjustment();
   }
   return typename Traits::Address(
       Traits::RegisterSet::getEncodedGPR(BaseRegNum), Offset);
 }
 
 /// Helper function for addProlog().
 ///
-/// This assumes Arg is an argument passed on the stack.  This sets the
-/// frame offset for Arg and updates InArgsSizeBytes according to Arg's
-/// width.  For an I64 arg that has been split into Lo and Hi components,
-/// it calls itself recursively on the components, taking care to handle
-/// Lo first because of the little-endian architecture.  Lastly, this
-/// function generates an instruction to copy Arg into its assigned
-/// register if applicable.
+/// This assumes Arg is an argument passed on the stack. This sets the frame
+/// offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
+/// I64 arg that has been split into Lo and Hi components, it calls itself
+/// recursively on the components, taking care to handle Lo first because of the
+/// little-endian architecture. Lastly, this function generates an instruction
+/// to copy Arg into its assigned register if applicable.
 template <class Machine>
 void TargetX86Base<Machine>::finishArgumentLowering(Variable *Arg,
                                                     Variable *FramePtr,
                                                     size_t BasicFrameOffset,
                                                     size_t &InArgsSizeBytes) {
   Variable *Lo = Arg->getLo();
   Variable *Hi = Arg->getHi();
   Type Ty = Arg->getType();
   if (!Traits::Is64Bit && Lo && Hi && Ty == IceType_i64) {
     assert(Lo->getType() != IceType_i64); // don't want infinite recursion
@@ skipping 10 matching lines @@
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64 || Traits::Is64Bit);
     typename Traits::X86OperandMem *Mem = Traits::X86OperandMem::create(
         Func, Ty, FramePtr, Ctx->getConstantInt32(Arg->getStackOffset()));
     if (isVectorType(Arg->getType())) {
       _movp(Arg, Mem);
     } else {
       _mov(Arg, Mem);
     }
     // This argument-copying instruction uses an explicit Traits::X86OperandMem
-    // operand instead of a Variable, so its fill-from-stack operation has to be
-    // tracked separately for statistics.
+    // operand instead of a Variable, so its fill-from-stack operation has to
+    // be tracked separately for statistics.
     Ctx->statsUpdateFills();
   }
 }
 
 template <class Machine> Type TargetX86Base<Machine>::stackSlotType() {
   return Traits::WordType;
 }
 
 template <class Machine>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, void>::type
 TargetX86Base<Machine>::split64(Variable *Var) {
   switch (Var->getType()) {
   default:
     return;
   case IceType_i64:
-  // TODO: Only consider F64 if we need to push each half when
-  // passing as an argument to a function call.  Note that each half
-  // is still typed as I32.
+  // TODO: Only consider F64 if we need to push each half when passing as an
+  // argument to a function call. Note that each half is still typed as I32.
   case IceType_f64:
     break;
   }
   Variable *Lo = Var->getLo();
   Variable *Hi = Var->getHi();
   if (Lo) {
     assert(Hi);
     return;
   }
   assert(Hi == nullptr);
@@ skipping 86 matching lines @@
 template <class Machine>
 llvm::SmallBitVector
 TargetX86Base<Machine>::getRegisterSet(RegSetMask Include,
                                        RegSetMask Exclude) const {
   return Traits::getRegisterSet(Include, Exclude);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerAlloca(const InstAlloca *Inst) {
   IsEbpBasedFrame = true;
-  // Conservatively require the stack to be aligned.  Some stack
-  // adjustment operations implemented below assume that the stack is
-  // aligned before the alloca.  All the alloca code ensures that the
-  // stack alignment is preserved after the alloca.  The stack alignment
-  // restriction can be relaxed in some cases.
+  // Conservatively require the stack to be aligned. Some stack adjustment
+  // operations implemented below assume that the stack is aligned before the
+  // alloca. All the alloca code ensures that the stack alignment is preserved
+  // after the alloca. The stack alignment restriction can be relaxed in some
+  // cases.
   NeedsStackAlignment = true;
 
   // TODO(stichnot): minimize the number of adjustments of esp, etc.
   Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
   Variable *Dest = Inst->getDest();
   uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   AlignmentParam = std::max(AlignmentParam, 1u);
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
 
   uint32_t Alignment =
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   if (Alignment > Traits::X86_STACK_ALIGNMENT_BYTES) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     uint32_t Value = ConstantTotalSize->getValue();
     Value = Utils::applyAlignment(Value, Alignment);
     _sub(esp, Ctx->getConstantInt32(Value));
   } else {
-    // Non-constant sizes need to be adjusted to the next highest
-    // multiple of the required alignment at runtime.
+    // Non-constant sizes need to be adjusted to the next highest multiple of
+    // the required alignment at runtime.
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
     _sub(esp, T);
   }
   _mov(Dest, esp);
 }
 
-/// Strength-reduce scalar integer multiplication by a constant (for
-/// i32 or narrower) for certain constants.  The lea instruction can be
-/// used to multiply by 3, 5, or 9, and the lsh instruction can be used
-/// to multiply by powers of 2.  These can be combined such that
-/// e.g. multiplying by 100 can be done as 2 lea-based multiplies by 5,
-/// combined with left-shifting by 2.
+/// Strength-reduce scalar integer multiplication by a constant (for i32 or
+/// narrower) for certain constants. The lea instruction can be used to multiply
+/// by 3, 5, or 9, and the lsh instruction can be used to multiply by powers of
+/// 2. These can be combined such that e.g. multiplying by 100 can be done as 2
+/// lea-based multiplies by 5, combined with left-shifting by 2.
 template <class Machine>
 bool TargetX86Base<Machine>::optimizeScalarMul(Variable *Dest, Operand *Src0,
                                                int32_t Src1) {
-  // Disable this optimization for Om1 and O0, just to keep things
-  // simple there.
+  // Disable this optimization for Om1 and O0, just to keep things simple
+  // there.
   if (Ctx->getFlags().getOptLevel() < Opt_1)
     return false;
   Type Ty = Dest->getType();
   Variable *T = nullptr;
   if (Src1 == -1) {
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
     return true;
   }
@@ skipping 35 matching lines @@
         ++CountOps;
       ++Count2;
       Src1 /= 2;
     } else {
       return false;
     }
   }
   // Lea optimization only works for i16 and i32 types, not i8.
   if (Ty != IceType_i16 && Ty != IceType_i32 && (Count3 || Count5 || Count9))
     return false;
-  // Limit the number of lea/shl operations for a single multiply, to
-  // a somewhat arbitrary choice of 3.
+  // Limit the number of lea/shl operations for a single multiply, to a
+  // somewhat arbitrary choice of 3.
   const uint32_t MaxOpsForOptimizedMul = 3;
   if (CountOps > MaxOpsForOptimizedMul)
     return false;
   _mov(T, Src0);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   for (uint32_t i = 0; i < Count9; ++i) {
     const uint16_t Shift = 3; // log2(9-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
     _set_dest_nonkillable();
@@ skipping 25 matching lines @@
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   if (Inst->isCommutative()) {
     if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1))
       std::swap(Src0, Src1);
     if (llvm::isa<Constant>(Src0) && !llvm::isa<Constant>(Src1))
       std::swap(Src0, Src1);
   }
   if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
     // These x86-32 helper-call-involved instructions are lowered in this
-    // separate switch. This is because loOperand() and hiOperand()
-    // may insert redundant instructions for constant blinding and
-    // pooling. Such redundant instructions will fail liveness analysis
-    // under -Om1 setting. And, actually these arguments do not need
-    // to be processed with loOperand() and hiOperand() to be used.
+    // separate switch. This is because loOperand() and hiOperand() may insert
+    // redundant instructions for constant blinding and pooling. Such redundant
+    // instructions will fail liveness analysis under -Om1 setting. And,
+    // actually these arguments do not need to be processed with loOperand()
+    // and hiOperand() to be used.
     switch (Inst->getOp()) {
     case InstArithmetic::Udiv: {
       const SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(H_udiv_i64, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       Call->addArg(Inst->getSrc(1));
       lowerCall(Call);
       return;
     }
     case InstArithmetic::Sdiv: {
@@ skipping 90 matching lines @@
       //   t4.hi += t2
       //   a.hi = t4.hi
       // The mul instruction cannot take an immediate operand.
       Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem);
       _mov(T_1, Src0Hi);
       _imul(T_1, Src1Lo);
       _mov(T_2, Src1Hi);
       _imul(T_2, Src0Lo);
       _mov(T_3, Src0Lo, Traits::RegisterSet::Reg_eax);
       _mul(T_4Lo, T_3, Src1Lo);
-      // The mul instruction produces two dest variables, edx:eax.  We
-      // create a fake definition of edx to account for this.
+      // The mul instruction produces two dest variables, edx:eax. We create a
+      // fake definition of edx to account for this.
       Context.insert(InstFakeDef::create(Func, T_4Hi, T_4Lo));
       _mov(DestLo, T_4Lo);
       _add(T_4Hi, T_1);
       _add(T_4Hi, T_2);
       _mov(DestHi, T_4Hi);
     } break;
     case InstArithmetic::Shl: {
       // TODO: Refactor the similarities between Shl, Lshr, and Ashr.
       // gcc does the following:
       // a=b<<c ==>
@@ skipping 15 matching lines @@
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       typename Traits::Insts::Label *Label =
           Traits::Insts::Label::create(Func, this);
       _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shld(T_3, T_2, T_1);
       _shl(T_2, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the
-      // intra-block control flow, so we need the _mov_nonkillable
-      // variant to avoid liveness problems.
+      // T_2 and T_3 are being assigned again because of the intra-block
+      // control flow, so we need the _mov_nonkillable variant to avoid
+      // liveness problems.
       _mov_nonkillable(T_3, T_2);
       _mov_nonkillable(T_2, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Lshr: {
       // a=b>>c (unsigned) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
@@ skipping 13 matching lines @@
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       typename Traits::Insts::Label *Label =
           Traits::Insts::Label::create(Func, this);
       _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _shr(T_3, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the
-      // intra-block control flow, so we need the _mov_nonkillable
-      // variant to avoid liveness problems.
+      // T_2 and T_3 are being assigned again because of the intra-block
+      // control flow, so we need the _mov_nonkillable variant to avoid
+      // liveness problems.
       _mov_nonkillable(T_2, T_3);
       _mov_nonkillable(T_3, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
@@ skipping 13 matching lines @@
       Constant *SignExtend = Ctx->getConstantInt32(0x1f);
       typename Traits::Insts::Label *Label =
           Traits::Insts::Label::create(Func, this);
       _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _sar(T_3, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the
-      // intra-block control flow, so T_2 needs the _mov_nonkillable
-      // variant to avoid liveness problems.  T_3 doesn't need special
-      // treatment because it is reassigned via _sar instead of _mov.
+      // T_2 and T_3 are being assigned again because of the intra-block
+      // control flow, so T_2 needs the _mov_nonkillable variant to avoid
+      // liveness problems. T_3 doesn't need special treatment because it is
+      // reassigned via _sar instead of _mov.
       _mov_nonkillable(T_2, T_3);
       _sar(T_3, SignExtend);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Fadd:
     case InstArithmetic::Fsub:
     case InstArithmetic::Fmul:
     case InstArithmetic::Fdiv:
     case InstArithmetic::Frem:
       llvm_unreachable("FP instruction with i64 type");
       break;
     case InstArithmetic::Udiv:
     case InstArithmetic::Sdiv:
     case InstArithmetic::Urem:
     case InstArithmetic::Srem:
       llvm_unreachable("Call-helper-involved instruction for i64 type \
                        should have already been handled before");
       break;
     }
     return;
   }
   if (isVectorType(Dest->getType())) {
-    // TODO: Trap on integer divide and integer modulo by zero.
-    // See: https://code.google.com/p/nativeclient/issues/detail?id=3899
+    // TODO: Trap on integer divide and integer modulo by zero. See:
+    // https://code.google.com/p/nativeclient/issues/detail?id=3899
     if (llvm::isa<typename Traits::X86OperandMem>(Src1))
       Src1 = legalizeToReg(Src1);
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add: {
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _padd(T, Src1);
@@ skipping 144 matching lines @@
   case InstArithmetic::Sub:
     _mov(T, Src0);
     _sub(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Mul:
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
       if (optimizeScalarMul(Dest, Src0, C->getValue()))
         return;
     }
-    // The 8-bit version of imul only allows the form "imul r/m8"
-    // where T must be in eax.
+    // The 8-bit version of imul only allows the form "imul r/m8" where T must
+    // be in eax.
     if (isByteSizedArithType(Dest->getType())) {
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     } else {
       _mov(T, Src0);
     }
     _imul(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Shl:
@@ skipping 39 matching lines @@
       Context.insert(InstFakeUse::create(Func, T_eax));
     } else {
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _mov(T_edx, Zero, Traits::RegisterSet::Reg_edx);
       _div(T, Src1, T_edx);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Sdiv:
-    // TODO(stichnot): Enable this after doing better performance
-    // and cross testing.
+    // TODO(stichnot): Enable this after doing better performance and cross
+    // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
-      // Optimize division by constant power of 2, but not for Om1
-      // or O0, just to keep things simple there.
+      // Optimize division by constant power of 2, but not for Om1 or O0, just
+      // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         int32_t Divisor = C->getValue();
         uint32_t UDivisor = static_cast<uint32_t>(Divisor);
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           Type Ty = Dest->getType();
           // LLVM does the following for dest=src/(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   sar t,log
           //   dest=t
           uint32_t TypeWidth = Traits::X86_CHAR_BIT * typeWidthInBytes(Ty);
           _mov(T, Src0);
-          // If for some reason we are dividing by 1, just treat it
-          // like an assignment.
+          // If for some reason we are dividing by 1, just treat it like an
+          // assignment.
           if (LogDiv > 0) {
             // The initial sar is unnecessary when dividing by 2.
             if (LogDiv > 1)
               _sar(T, Ctx->getConstantInt(Ty, TypeWidth - 1));
             _shr(T, Ctx->getConstantInt(Ty, TypeWidth - LogDiv));
             _add(T, Src0);
             _sar(T, Ctx->getConstantInt(Ty, LogDiv));
           }
           _mov(Dest, T);
           return;
@@ skipping 34 matching lines @@
     } else {
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       T_edx = makeReg(Dest->getType(), Traits::RegisterSet::Reg_edx);
       _mov(T_edx, Zero);
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _div(T_edx, Src1, T);
       _mov(Dest, T_edx);
     }
     break;
   case InstArithmetic::Srem:
-    // TODO(stichnot): Enable this after doing better performance
-    // and cross testing.
+    // TODO(stichnot): Enable this after doing better performance and cross
+    // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
-      // Optimize mod by constant power of 2, but not for Om1 or O0,
-      // just to keep things simple there.
+      // Optimize mod by constant power of 2, but not for Om1 or O0, just to
+      // keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         int32_t Divisor = C->getValue();
         uint32_t UDivisor = static_cast<uint32_t>(Divisor);
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           Type Ty = Dest->getType();
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
@@ skipping 96 matching lines @@
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
     Operand *Src0Legal;
     if (Dest->hasReg()) {
       // If Dest already has a physical register, then only basic legalization
       // is needed, as the source operand can be a register, immediate, or
       // memory.
       Src0Legal = legalize(Src0);
     } else {
-      // If Dest could be a stack operand, then RI must be a physical
-      // register or a scalar integer immediate.
+      // If Dest could be a stack operand, then RI must be a physical register
+      // or a scalar integer immediate.
       Src0Legal = legalize(Src0, Legal_Reg | Legal_Imm);
     }
     if (isVectorType(Dest->getType()))
       _movp(Dest, Src0Legal);
     else
       _mov(Dest, Src0Legal);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
     return;
   }
   Operand *Cond = Inst->getCondition();
 
   // Handle folding opportunities.
   if (const class Inst *Producer = FoldingInfo.getProducerFor(Cond)) {
     assert(Producer->isDeleted());
     switch (BoolFolding::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding::PK_Icmp32: {
-      // TODO(stichnot): Refactor similarities between this block and
-      // the corresponding code in lowerIcmp().
+      // TODO(stichnot): Refactor similarities between this block and the
+      // corresponding code in lowerIcmp().
       auto *Cmp = llvm::dyn_cast<InstIcmp>(Producer);
       Operand *Src0 = Producer->getSrc(0);
       Operand *Src1 = legalize(Producer->getSrc(1));
       Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
       _cmp(Src0RM, Src1);
       _br(Traits::getIcmp32Mapping(Cmp->getCondition()), Inst->getTargetTrue(),
           Inst->getTargetFalse());
       return;
     }
     }
@@ skipping 10 matching lines @@
   // a = cast(b) ==> t=cast(b); a=t; (link t->b, link a->t, no overlap)
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     // Src0RM is the source operand legalized to physical register or memory,
     // but not immediate, since the relevant x86 native instructions don't
-    // allow an immediate operand.  If the operand is an immediate, we could
-    // consider computing the strength-reduced result at translation time,
-    // but we're unlikely to see something like that in the bitcode that
-    // the optimizer wouldn't have already taken care of.
+    // allow an immediate operand. If the operand is an immediate, we could
+    // consider computing the strength-reduced result at translation time, but
+    // we're unlikely to see something like that in the bitcode that the
+    // optimizer wouldn't have already taken care of.
     Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
     if (isVectorType(Dest->getType())) {
       Type DestTy = Dest->getType();
       if (DestTy == IceType_v16i8) {
         // onemask = materialize(1,1,...); dst = (src & onemask) > 0
         Variable *OneMask = makeVectorOfOnes(Dest->getType());
         Variable *T = makeReg(DestTy);
         _movp(T, Src0RM);
         _pand(T, OneMask);
         Variable *Zeros = makeVectorOfZeros(Dest->getType());
@@ skipping 39 matching lines @@
       // sar t1, dst_bitwidth - 1
       // dst = t1
       size_t DestBits =
           Traits::X86_CHAR_BIT * typeWidthInBytes(Dest->getType());
       Constant *ShiftAmount = Ctx->getConstantInt32(DestBits - 1);
       Variable *T = makeReg(Dest->getType());
       if (typeWidthInBytes(Dest->getType()) <=
           typeWidthInBytes(Src0RM->getType())) {
         _mov(T, Src0RM);
       } else {
-        // Widen the source using movsx or movzx.  (It doesn't matter
-        // which one, since the following shl/sar overwrite the bits.)
+        // Widen the source using movsx or movzx. (It doesn't matter which one,
+        // since the following shl/sar overwrite the bits.)
         _movzx(T, Src0RM);
       }
       _shl(T, ShiftAmount);
       _sar(T, ShiftAmount);
       _mov(Dest, T);
     } else {
       // t1 = movsx src; dst = t1
       Variable *T = makeReg(Dest->getType());
       _movsx(T, Src0RM);
       _mov(Dest, T);
@@ skipping 90 matching lines @@
     if (isVectorType(Dest->getType())) {
       assert(Dest->getType() == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
-      // Use a helper for converting floating-point values to 64-bit
-      // integers.  SSE2 appears to have no way to convert from xmm
-      // registers to something like the edx:eax register pair, and
-      // gcc and clang both want to use x87 instructions complete with
-      // temporary manipulation of the status word.  This helper is
-      // not needed for x86-64.
+      // Use a helper for converting floating-point values to 64-bit integers.
+      // SSE2 appears to have no way to convert from xmm registers to something
+      // like the edx:eax register pair, and gcc and clang both want to use x87
+      // instructions complete with temporary manipulation of the status word.
+      // This helper is not needed for x86-64.
       split64(Dest);
       const SizeT MaxSrcs = 1;
       Type SrcType = Inst->getSrc(0)->getType();
       InstCall *Call =
           makeHelperCall(isFloat32Asserting32Or64(SrcType) ? H_fptosi_f32_i64
                                                            : H_fptosi_f64_i64,
                          Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
     } else {
@@ skipping 114 matching lines @@
     Operand *Src0 = Inst->getSrc(0);
     if (isVectorType(Src0->getType())) {
       assert(Dest->getType() == IceType_v4f32 &&
              Src0->getType() == IceType_v4i32);
       const SizeT MaxSrcs = 1;
       InstCall *Call = makeHelperCall(H_uitofp_4xi32_4xf32, Dest, MaxSrcs);
       Call->addArg(Src0);
       lowerCall(Call);
     } else if (Src0->getType() == IceType_i64 ||
                (!Traits::Is64Bit && Src0->getType() == IceType_i32)) {
-      // Use a helper for x86-32 and x86-64.  Also use a helper for
-      // i32 on x86-32.
+      // Use a helper for x86-32 and x86-64. Also use a helper for i32 on
+      // x86-32.
       const SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       IceString TargetString;
       if (isInt32Asserting32Or64(Src0->getType())) {
         TargetString = isFloat32Asserting32Or64(DestType) ? H_uitofp_i32_f32
                                                           : H_uitofp_i32_f64;
       } else {
         TargetString = isFloat32Asserting32Or64(DestType) ? H_uitofp_i64_f32
                                                           : H_uitofp_i64_f64;
       }
@@ skipping 113 matching lines @@
         _mov(DestLo, T_Lo);
         _mov(T_Hi, SpillHi);
         _mov(DestHi, T_Hi);
       }
     } break;
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       if (Traits::Is64Bit) {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         Variable *T = makeReg(IceType_f64);
-        // Movd requires its fp argument (in this case, the bitcast destination)
-        // to be an xmm register.
+        // Movd requires its fp argument (in this case, the bitcast
+        // destination) to be an xmm register.
         T->setMustHaveReg();
         _movd(T, Src0RM);
         _mov(Dest, T);
       } else {
         Src0 = legalize(Src0);
         if (llvm::isa<typename Traits::X86OperandMem>(Src0)) {
           Variable *T = Func->makeVariable(Dest->getType());
           _movq(T, Src0);
           _movq(Dest, T);
           break;
@@ skipping 11 matching lines @@
         Variable *Spill = SpillVar;
         Spill->setMustNotHaveReg();
 
         Variable *T_Lo = nullptr, *T_Hi = nullptr;
         typename Traits::VariableSplit *SpillLo = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::Low);
         typename Traits::VariableSplit *SpillHi = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::High);
         _mov(T_Lo, loOperand(Src0));
         // Technically, the Spill is defined after the _store happens, but
-        // SpillLo is considered a "use" of Spill so define Spill before it
-        // is used.
+        // SpillLo is considered a "use" of Spill so define Spill before it is
+        // used.
         Context.insert(InstFakeDef::create(Func, Spill));
         _store(T_Lo, SpillLo);
         _mov(T_Hi, hiOperand(Src0));
         _store(T_Hi, SpillHi);
         _movq(Dest, Spill);
       }
     } break;
     case IceType_v8i1: {
       assert(Src0->getType() == IceType_i8);
       InstCall *Call = makeHelperCall(H_bitcast_i8_8xi1, Dest, 1);
@@ skipping 44 matching lines @@
                      InstructionSet >= Traits::SSE4_1;
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
     Variable *SourceVectR = legalizeToReg(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
     Variable *T = nullptr;
     if (Index) {
-      // The shuffle only needs to occur if the element to be extracted
-      // is not at the lowest index.
+      // The shuffle only needs to occur if the element to be extracted is not
+      // at the lowest index.
       Constant *Mask = Ctx->getConstantInt32(Index);
       T = makeReg(Ty);
       _pshufd(T, legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem), Mask);
     } else {
       T = legalizeToReg(SourceVectNotLegalized);
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElementR, T);
     } else { // Ty == IceType_f32
-      // TODO(wala): _movss is only used here because _mov does not
-      // allow a vector source and a scalar destination.  _mov should be
-      // able to be used here.
-      // _movss is a binary instruction, so the FakeDef is needed to
-      // keep the live range analysis consistent.
+      // TODO(wala): _movss is only used here because _mov does not allow a
+      // vector source and a scalar destination.  _mov should be able to be
+      // used here.
+      // _movss is a binary instruction, so the FakeDef is needed to keep the
+      // live range analysis consistent.
       Context.insert(InstFakeDef::create(Func, ExtractedElementR));
       _movss(ExtractedElementR, T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
     //
-    // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
-    // support for legalizing to mem is implemented.
+    // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
+    // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
     _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _mov(ExtractedElementR, Loc);
   }
@@ skipping 159 matching lines @@
       Src0 = NewSrc0;
       Src1 = NewSrc1;
       Ty = NewTy;
     }
 
     InstIcmp::ICond Condition = Inst->getCondition();
 
     Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
 
-    // SSE2 only has signed comparison operations.  Transform unsigned
-    // inputs in a manner that allows for the use of signed comparison
-    // operations by flipping the high order bits.
+    // SSE2 only has signed comparison operations. Transform unsigned inputs in
+    // a manner that allows for the use of signed comparison operations by
+    // flipping the high order bits.
     if (Condition == InstIcmp::Ugt || Condition == InstIcmp::Uge ||
         Condition == InstIcmp::Ult || Condition == InstIcmp::Ule) {
       Variable *T0 = makeReg(Ty);
       Variable *T1 = makeReg(Ty);
       Variable *HighOrderBits = makeVectorOfHighOrderBits(Ty);
       _movp(T0, Src0RM);
       _pxor(T0, HighOrderBits);
       _movp(T1, Src1RM);
       _pxor(T1, HighOrderBits);
       Src0RM = T0;
@@ skipping 114 matching lines @@
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
-    // Expand the element to the appropriate size for it to be inserted
-    // in the vector.
+    // Expand the element to the appropriate size for it to be inserted in the
+    // vector.
     Variable *Expanded = Func->makeVariable(InVectorElementTy);
     InstCast *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
                                       ElementToInsertNotLegalized);
     lowerCast(Cast);
     ElementToInsertNotLegalized = Expanded;
   }
 
   if (Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
       InstructionSet >= Traits::SSE4_1) {
     // Use insertps, pinsrb, pinsrw, or pinsrd.
@@ skipping 25 matching lines @@
     }
 
     if (Index == 0) {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectRM);
       _movss(T, ElementR);
       _movp(Inst->getDest(), T);
       return;
     }
 
-    // shufps treats the source and desination operands as vectors of
-    // four doublewords.  The destination's two high doublewords are
-    // selected from the source operand and the two low doublewords are
-    // selected from the (original value of) the destination operand.
-    // An insertelement operation can be effected with a sequence of two
-    // shufps operations with appropriate masks.  In all cases below,
-    // Element[0] is being inserted into SourceVectOperand.  Indices are
-    // ordered from left to right.
+    // shufps treats the source and desination operands as vectors of four

[Jim Stichnoth, 2015/09/16 00:01:29]

destination

[ascull, 2015/09/16 18:30:09]

Done.

+    // doublewords.  The destination's two high doublewords are selected from
+    // the source operand and the two low doublewords are selected from the
+    // (original value of) the destination operand. An insertelement operation
+    // can be effected with a sequence of two shufps operations with
+    // appropriate masks.  In all cases below, Element[0] is being inserted
+    // into SourceVectOperand.  Indices are ordered from left to right.
     //
     // insertelement into index 1 (result is stored in ElementR):
     //   ElementR := ElementR[0, 0] SourceVectRM[0, 0]
     //   ElementR := ElementR[3, 0] SourceVectRM[2, 3]
     //
     // insertelement into index 2 (result is stored in T):
     //   T := SourceVectRM
     //   ElementR := ElementR[0, 0] T[0, 3]
     //   T := T[0, 1] ElementR[0, 3]
     //
@@ skipping 13 matching lines @@
       _movp(Inst->getDest(), ElementR);
     } else {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectRM);
       _shufps(ElementR, T, Mask1Constant);
       _shufps(T, ElementR, Mask2Constant);
       _movp(Inst->getDest(), T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
-    // Spill the value to a stack slot and perform the insertion in
-    // memory.
+    // Spill the value to a stack slot and perform the insertion in memory.
     //
-    // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
-    // support for legalizing to mem is implemented.
+    // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
+    // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
     _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _store(legalizeToReg(ElementToInsertNotLegalized), Loc);
 
@@ skipping 25 matching lines @@
   }
   case Intrinsics::AtomicFence:
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(0)))) {
       Func->setError("Unexpected memory ordering for AtomicFence");
       return;
     }
     _mfence();
     return;
   case Intrinsics::AtomicFenceAll:
-    // NOTE: FenceAll should prevent and load/store from being moved
-    // across the fence (both atomic and non-atomic). The InstX8632Mfence
-    // instruction is currently marked coarsely as "HasSideEffects".
+    // NOTE: FenceAll should prevent and load/store from being moved across the
+    // fence (both atomic and non-atomic). The InstX8632Mfence instruction is
+    // currently marked coarsely as "HasSideEffects".
     _mfence();
     return;
   case Intrinsics::AtomicIsLockFree: {
     // X86 is always lock free for 8/16/32/64 bit accesses.
-    // TODO(jvoung): Since the result is constant when given a constant
-    // byte size, this opens up DCE opportunities.
+    // TODO(jvoung): Since the result is constant when given a constant byte
+    // size, this opens up DCE opportunities.
     Operand *ByteSize = Instr->getArg(0);
     Variable *Dest = Instr->getDest();
     if (ConstantInteger32 *CI = llvm::dyn_cast<ConstantInteger32>(ByteSize)) {
       Constant *Result;
       switch (CI->getValue()) {
       default:
-        // Some x86-64 processors support the cmpxchg16b intruction, which
-        // can make 16-byte operations lock free (when used with the LOCK
-        // prefix). However, that's not supported in 32-bit mode, so just
-        // return 0 even for large sizes.
+        // Some x86-64 processors support the cmpxchg16b intruction, which can

[Jim Stichnoth, 2015/09/16 00:01:29]

instruction

[ascull, 2015/09/16 18:30:09]

Done.

+        // make 16-byte operations lock free (when used with the LOCK prefix).
+        // However, that's not supported in 32-bit mode, so just return 0 even
+        // for large sizes.
         Result = Ctx->getConstantZero(IceType_i32);
         break;
       case 1:
       case 2:
       case 4:
       case 8:
         Result = Ctx->getConstantInt32(1);
         break;
       }
       _mov(Dest, Result);
       return;
     }
     // The PNaCl ABI requires the byte size to be a compile-time constant.
     Func->setError("AtomicIsLockFree byte size should be compile-time const");
     return;
   }
   case Intrinsics::AtomicLoad: {
-    // We require the memory address to be naturally aligned.
-    // Given that is the case, then normal loads are atomic.
+    // We require the memory address to be naturally aligned. Given that is the
+    // case, then normal loads are atomic.
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(1)))) {
       Func->setError("Unexpected memory ordering for AtomicLoad");
       return;
     }
     Variable *Dest = Instr->getDest();
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       // Follow what GCC does and use a movq instead of what lowerLoad()
-      // normally does (split the load into two).
-      // Thus, this skips load/arithmetic op folding. Load/arithmetic folding
-      // can't happen anyway, since this is x86-32 and integer arithmetic only
-      // happens on 32-bit quantities.
+      // normally does (split the load into two). Thus, this skips
+      // load/arithmetic op folding. Load/arithmetic folding can't happen
+      // anyway, since this is x86-32 and integer arithmetic only happens on
+      // 32-bit quantities.
       Variable *T = makeReg(IceType_f64);
       typename Traits::X86OperandMem *Addr =
           formMemoryOperand(Instr->getArg(0), IceType_f64);
       _movq(T, Addr);
       // Then cast the bits back out of the XMM register to the i64 Dest.
       InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
       lowerCast(Cast);
       // Make sure that the atomic load isn't elided when unused.
       Context.insert(InstFakeUse::create(Func, Dest->getLo()));
       Context.insert(InstFakeUse::create(Func, Dest->getHi()));
       return;
     }
     InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
     lowerLoad(Load);
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
-    // Since lowerLoad may fuse the load w/ an arithmetic instruction,
-    // insert the FakeUse on the last-inserted instruction's dest.
+    // Since lowerLoad may fuse the load w/ an arithmetic instruction, insert
+    // the FakeUse on the last-inserted instruction's dest.
     Context.insert(
         InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)))) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
     lowerAtomicRMW(
         Instr->getDest(),
         static_cast<uint32_t>(
             llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
         Instr->getArg(1), Instr->getArg(2));
     return;
   case Intrinsics::AtomicStore: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(2)))) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }
-    // We require the memory address to be naturally aligned.
-    // Given that is the case, then normal stores are atomic.
-    // Add a fence after the store to make it visible.
+    // We require the memory address to be naturally aligned. Given that is the
+    // case, then normal stores are atomic. Add a fence after the store to make
+    // it visible.
     Operand *Value = Instr->getArg(0);
     Operand *Ptr = Instr->getArg(1);
     if (!Traits::Is64Bit && Value->getType() == IceType_i64) {
-      // Use a movq instead of what lowerStore() normally does
-      // (split the store into two), following what GCC does.
-      // Cast the bits from int -> to an xmm register first.
+      // Use a movq instead of what lowerStore() normally does (split the store
+      // into two), following what GCC does. Cast the bits from int -> to an
+      // xmm register first.
       Variable *T = makeReg(IceType_f64);
       InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, T, Value);
       lowerCast(Cast);
       // Then store XMM w/ a movq.
       typename Traits::X86OperandMem *Addr =
           formMemoryOperand(Ptr, IceType_f64);
       _storeq(T, Addr);
       _mfence();
       return;
     }
     InstStore *Store = InstStore::create(Func, Value, Ptr);
     lowerStore(Store);
     _mfence();
     return;
   }
   case Intrinsics::Bswap: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
-    // In 32-bit mode, bswap only works on 32-bit arguments, and the
-    // argument must be a register. Use rotate left for 16-bit bswap.
+    // In 32-bit mode, bswap only works on 32-bit arguments, and the argument
+    // must be a register. Use rotate left for 16-bit bswap.
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
       Variable *T_Lo = legalizeToReg(loOperand(Val));
       Variable *T_Hi = legalizeToReg(hiOperand(Val));
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _bswap(T_Lo);
       _bswap(T_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
@@ skipping 68 matching lines @@
       // another 64-bit wide.)
       Variable *T_1 = makeReg(IceType_i32);
       _mov(T_1, T);
       Variable *T_2 = makeReg(IceType_i64);
       _movzx(T_2, T_1);
       _mov(Dest, T_2);
     }
     return;
   }
   case Intrinsics::Ctlz: {
-    // The "is zero undef" parameter is ignored and we always return
-    // a well-defined value.
+    // The "is zero undef" parameter is ignored and we always return a
+    // well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
     Operand *SecondVal = nullptr;
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       FirstVal = loOperand(Val);
       SecondVal = hiOperand(Val);
     } else {
       FirstVal = Val;
     }
     const bool IsCttz = false;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Cttz: {
-    // The "is zero undef" parameter is ignored and we always return
-    // a well-defined value.
+    // The "is zero undef" parameter is ignored and we always return a
+    // well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
     Operand *SecondVal = nullptr;
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       FirstVal = hiOperand(Val);
       SecondVal = loOperand(Val);
     } else {
       FirstVal = Val;
     }
     const bool IsCttz = true;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Fabs: {
     Operand *Src = legalize(Instr->getArg(0));
     Type Ty = Src->getType();
     Variable *Dest = Instr->getDest();
     Variable *T = makeVectorOfFabsMask(Ty);
-    // The pand instruction operates on an m128 memory operand, so if
-    // Src is an f32 or f64, we need to make sure it's in a register.
+    // The pand instruction operates on an m128 memory operand, so if Src is an
+    // f32 or f64, we need to make sure it's in a register.
     if (isVectorType(Ty)) {
       if (llvm::isa<typename Traits::X86OperandMem>(Src))
         Src = legalizeToReg(Src);
     } else {
       Src = legalizeToReg(Src);
     }
     _pand(T, Src);
     if (isVectorType(Ty))
       _movp(Dest, T);
     else
@@ skipping 564 matching lines @@
 
     Variable *SrcBase = legalizeToReg(Src);
     Variable *DestBase = legalizeToReg(Dest);
 
     std::tuple<Type, Constant *, Variable *>
         Moves[Traits::MEMMOVE_UNROLL_LIMIT];
     Constant *Offset;
     Variable *Reg;
 
     // Copy the data into registers as the source and destination could overlap
-    // so make sure not to clobber the memory. This also means overlapping moves
-    // can be used as we are taking a safe snapshot of the memory.
+    // so make sure not to clobber the memory. This also means overlapping
+    // moves can be used as we are taking a safe snapshot of the memory.
     Type Ty = largestTypeInSize(CountValue);
     uint32_t TyWidth = typeWidthInBytes(Ty);
 
     uint32_t RemainingBytes = CountValue;
     int32_t OffsetAmt = (CountValue & ~(TyWidth - 1)) - TyWidth;
     size_t N = 0;
     while (RemainingBytes >= TyWidth) {
       assert(N <= Traits::MEMMOVE_UNROLL_LIMIT);
       Offset = Ctx->getConstantInt32(OffsetAmt);
       Reg = makeReg(Ty);
@@ skipping 180 matching lines @@
   Str << ", Index=";
   if (Index)
     Index->dump(Func);
   else
     Str << "<null>";
   Str << ", Shift=" << Shift << ", Offset=" << Offset << "\n";
 }
 
 inline bool matchTransitiveAssign(const VariablesMetadata *VMetadata,
                                   Variable *&Var, const Inst *&Reason) {
-  // Var originates from Var=SrcVar ==>
-  //   set Var:=SrcVar
+  // Var originates from Var=SrcVar ==> set Var:=SrcVar
   if (Var == nullptr)
     return false;
   if (const Inst *VarAssign = VMetadata->getSingleDefinition(Var)) {
     assert(!VMetadata->isMultiDef(Var));
     if (llvm::isa<InstAssign>(VarAssign)) {
       Operand *SrcOp = VarAssign->getSrc(0);
       assert(SrcOp);
       if (Variable *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
         if (!VMetadata->isMultiDef(SrcVar) &&
             // TODO: ensure SrcVar stays single-BB
@@ skipping 141 matching lines @@
   Func->resetCurrentNode();
   if (Func->isVerbose(IceV_AddrOpt)) {
     OstreamLocker L(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "\nStarting computeAddressOpt for instruction:\n  ";
     Instr->dumpDecorated(Func);
   }
   (void)Offset; // TODO: pattern-match for non-zero offsets.
   if (Base == nullptr)
     return;
-  // If the Base has more than one use or is live across multiple
-  // blocks, then don't go further.  Alternatively (?), never consider
-  // a transformation that would change a variable that is currently
-  // *not* live across basic block boundaries into one that *is*.
+  // If the Base has more than one use or is live across multiple blocks, then
+  // don't go further. Alternatively (?), never consider a transformation that
+  // would change a variable that is currently *not* live across basic block
+  // boundaries into one that *is*.
   if (Func->getVMetadata()->isMultiBlock(Base) /* || Base->getUseCount() > 1*/)
     return;
 
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   bool Continue = true;
   while (Continue) {
     const Inst *Reason = nullptr;
     if (matchTransitiveAssign(VMetadata, Base, Reason) ||
         matchTransitiveAssign(VMetadata, Index, Reason) ||
         matchCombinedBaseIndex(VMetadata, Base, Index, Shift, Reason) ||
@@ skipping 87 matching lines @@
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(DestTy)) {
     Type SrcTy = SrcT->getType();
     Variable *T = makeReg(SrcTy);
     Operand *SrcTRM = legalize(SrcT, Legal_Reg | Legal_Mem);
     Operand *SrcFRM = legalize(SrcF, Legal_Reg | Legal_Mem);
     if (InstructionSet >= Traits::SSE4_1) {
-      // TODO(wala): If the condition operand is a constant, use blendps
-      // or pblendw.
+      // TODO(wala): If the condition operand is a constant, use blendps or
+      // pblendw.
       //
       // Use blendvps or pblendvb to implement select.
       if (SrcTy == IceType_v4i1 || SrcTy == IceType_v4i32 ||
           SrcTy == IceType_v4f32) {
         Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
         Variable *xmm0 = makeReg(IceType_v4i32, Traits::RegisterSet::Reg_xmm0);
         _movp(xmm0, ConditionRM);
         _psll(xmm0, Ctx->getConstantInt8(31));
         _movp(T, SrcFRM);
         _blendvps(T, SrcTRM, xmm0);
@@ skipping 56 matching lines @@
   }
   if (CmpOpnd0 == nullptr) {
     CmpOpnd0 = legalize(Condition, Legal_Reg | Legal_Mem);
     CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
   }
   assert(CmpOpnd0);
   assert(CmpOpnd1);
 
   _cmp(CmpOpnd0, CmpOpnd1);
   if (typeWidthInBytes(DestTy) == 1 || isFloatingType(DestTy)) {
-    // The cmov instruction doesn't allow 8-bit or FP operands, so
-    // we need explicit control flow.
+    // The cmov instruction doesn't allow 8-bit or FP operands, so we need
+    // explicit control flow.
     // d=cmp e,f; a=d?b:c ==> cmp e,f; a=b; jne L1; a=c; L1:
     typename Traits::Insts::Label *Label =
         Traits::Insts::Label::create(Func, this);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm);
     _mov(Dest, SrcT);
     _br(Cond, Label);
     SrcF = legalize(SrcF, Legal_Reg | Legal_Imm);
     _mov_nonkillable(Dest, SrcF);
     Context.insert(Label);
     return;
   }
   // mov t, SrcF; cmov_cond t, SrcT; mov dest, t
-  // But if SrcT is immediate, we might be able to do better, as
-  // the cmov instruction doesn't allow an immediate operand:
+  // But if SrcT is immediate, we might be able to do better, as the cmov
+  // instruction doesn't allow an immediate operand:
   // mov t, SrcT; cmov_!cond t, SrcF; mov dest, t
   if (llvm::isa<Constant>(SrcT) && !llvm::isa<Constant>(SrcF)) {
     std::swap(SrcT, SrcF);
     Cond = InstX86Base<Machine>::getOppositeCondition(Cond);
   }
   if (!Traits::Is64Bit && DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
@@ skipping 339 matching lines @@
 
   lowerAssign(InstAssign::create(Func, Dest, T));
 }
 
 /// The following pattern occurs often in lowered C and C++ code:
 ///
 ///   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
 ///   %cmp.ext = sext <n x i1> %cmp to <n x ty>
 ///
 /// We can eliminate the sext operation by copying the result of pcmpeqd,
-/// pcmpgtd, or cmpps (which produce sign extended results) to the result
-/// of the sext operation.
+/// pcmpgtd, or cmpps (which produce sign extended results) to the result of the
+/// sext operation.
 template <class Machine>
 void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
     Variable *SignExtendedResult) {
   if (InstCast *NextCast =
           llvm::dyn_cast_or_null<InstCast>(Context.getNextInst())) {
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerUnreachable(
     const InstUnreachable * /*Inst*/) {
   _ud2();
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerRMW(
     const typename Traits::Insts::FakeRMW *RMW) {
-  // If the beacon variable's live range does not end in this
-  // instruction, then it must end in the modified Store instruction
-  // that follows.  This means that the original Store instruction is
-  // still there, either because the value being stored is used beyond
-  // the Store instruction, or because dead code elimination did not
-  // happen.  In either case, we cancel RMW lowering (and the caller
-  // deletes the RMW instruction).
+  // If the beacon variable's live range does not end in this instruction, then
+  // it must end in the modified Store instruction that follows. This means
+  // that the original Store instruction is still there, either because the
+  // value being stored is used beyond the Store instruction, or because dead
+  // code elimination did not happen. In either case, we cancel RMW lowering
+  // (and the caller deletes the RMW instruction).
   if (!RMW->isLastUse(RMW->getBeacon()))
     return;
   Operand *Src = RMW->getData();
   Type Ty = Src->getType();
   typename Traits::X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty);
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Src = legalizeUndef(Src);
     Operand *SrcLo = legalize(loOperand(Src), Legal_Reg | Legal_Imm);
     Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm);
     typename Traits::X86OperandMem *AddrLo =
@@ skipping 60 matching lines @@
 template <class Machine>
 void TargetX86Base<Machine>::lowerOther(const Inst *Instr) {
   if (const auto *RMW =
           llvm::dyn_cast<typename Traits::Insts::FakeRMW>(Instr)) {
     lowerRMW(RMW);
   } else {
     TargetLowering::lowerOther(Instr);
   }
 }
 
-/// Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
-/// preserve integrity of liveness analysis.  Undef values are also
-/// turned into zeroes, since loOperand() and hiOperand() don't expect
-/// Undef input.
+/// Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve
+/// integrity of liveness analysis. Undef values are also turned into zeroes,
+/// since loOperand() and hiOperand() don't expect Undef input.
 template <class Machine> void TargetX86Base<Machine>::prelowerPhis() {
   if (Traits::Is64Bit) {
     // On x86-64 we don't need to prelower phis -- the architecture can handle
     // 64-bit integer natively.
     return;
   }
 
-  // Pause constant blinding or pooling, blinding or pooling will be done
-  // later during phi lowering assignments
+  // Pause constant blinding or pooling, blinding or pooling will be done later
+  // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
   PhiLowering::prelowerPhis32Bit<TargetX86Base<Machine>>(
       this, Context.getNode(), Func);
 }
 
-// There is no support for loading or emitting vector constants, so the
-// vector values returned from makeVectorOfZeros, makeVectorOfOnes,
-// etc. are initialized with register operations.
+// There is no support for loading or emitting vector constants, so the vector
+// values returned from makeVectorOfZeros, makeVectorOfOnes, etc. are
+// initialized with register operations.
 //
-// TODO(wala): Add limited support for vector constants so that
-// complex initialization in registers is unnecessary.
+// TODO(wala): Add limited support for vector constants so that complex
+// initialization in registers is unnecessary.
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
-  // Insert a FakeDef, since otherwise the live range of Reg might
-  // be overestimated.
+  // Insert a FakeDef, since otherwise the live range of Reg might be
+  // overestimated.
   Context.insert(InstFakeDef::create(Func, Reg));
   _pxor(Reg, Reg);
   return Reg;
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfMinusOnes(Type Ty,
                                                         int32_t RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
@@ skipping 25 matching lines @@
     // SSE has no left shift operation for vectors of 8 bit integers.
     const uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
     _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
-/// Construct a mask in a register that can be and'ed with a
-/// floating-point value to mask off its sign bit.  The value will be
-/// <4 x 0x7fffffff> for f32 and v4f32, and <2 x 0x7fffffffffffffff>
-/// for f64.  Construct it as vector of ones logically right shifted
-/// one bit.  TODO(stichnot): Fix the wala TODO above, to represent
-/// vector constants in memory.
+/// Construct a mask in a register that can be and'ed with a floating-point
+/// value to mask off its sign bit. The value will be <4 x 0x7fffffff> for f32
+/// and v4f32, and <2 x 0x7fffffffffffffff> for f64. Construct it as vector of
+/// ones logically right shifted one bit.
+// TODO(stichnot): Fix the wala
+// TODO: above, to represent vector constants in memory.
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfFabsMask(Type Ty,
                                                        int32_t RegNum) {
   Variable *Reg = makeVectorOfMinusOnes(Ty, RegNum);
   _psrl(Reg, Ctx->getConstantInt8(1));
   return Reg;
 }
 
 template <class Machine>
 typename TargetX86Base<Machine>::Traits::X86OperandMem *
 TargetX86Base<Machine>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
                                                      uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->mustNotHaveReg());
   assert(Slot->getRegNum() == Variable::NoRegister);
   // Compute the location of Loc in memory.
-  // TODO(wala,stichnot): lea should not be required.  The address of
-  // the stack slot is known at compile time (although not until after
-  // addProlog()).
+  // TODO(wala,stichnot): lea should not
+  // be required. The address of the stack slot is known at compile time
+  // (although not until after addProlog()).
   const Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
   return Traits::X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
 }
 
 /// Helper for legalize() to emit the right code to lower an operand to a
 /// register of the appropriate type.
 template <class Machine>
 Variable *TargetX86Base<Machine>::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
                                           int32_t RegNum) {
   Type Ty = From->getType();
-  // Assert that a physical register is allowed.  To date, all calls
-  // to legalize() allow a physical register.  If a physical register
-  // needs to be explicitly disallowed, then new code will need to be
-  // written to force a spill.
+  // Assert that a physical register is allowed. To date, all calls to
+  // legalize() allow a physical register. If a physical register needs to be
+  // explicitly disallowed, then new code will need to be written to force a
+  // spill.
   assert(Allowed & Legal_Reg);
-  // If we're asking for a specific physical register, make sure we're
-  // not allowing any other operand kinds.  (This could be future
-  // work, e.g. allow the shl shift amount to be either an immediate
-  // or in ecx.)
+  // If we're asking for a specific physical register, make sure we're not
+  // allowing any other operand kinds. (This could be future work, e.g. allow
+  // the shl shift amount to be either an immediate or in ecx.)
   assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
 
   if (auto Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
-    // Before doing anything with a Mem operand, we need to ensure
-    // that the Base and Index components are in physical registers.
+    // Before doing anything with a Mem operand, we need to ensure that the
+    // Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = legalizeToReg(Base);
     }
     if (Index) {
       RegIndex = legalizeToReg(Index);
     }
@@ skipping 24 matching lines @@
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
         Variable *V = copyToReg(Const, RegNum);
         V->setMustHaveReg();
         return V;
       }
     }
 
-    // If the operand is an 32 bit constant integer, we should check
-    // whether we need to randomize it or pool it.
+    // If the operand is an 32 bit constant integer, we should check whether we
+    // need to randomize it or pool it.
     if (ConstantInteger32 *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
     }
 
-    // Convert a scalar floating point constant into an explicit
-    // memory operand.
+    // Convert a scalar floating point constant into an explicit memory
+    // operand.
     if (isScalarFloatingType(Ty)) {
       Variable *Base = nullptr;
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
       llvm::cast<Constant>(From)->emitPoolLabel(StrBuf);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
       From = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
     }
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm) && !isScalarFloatingType(Ty))
       // Immediate specifically not allowed
       NeedsReg = true;
     if (!(Allowed & Legal_Mem) && isScalarFloatingType(Ty))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   if (auto Var = llvm::dyn_cast<Variable>(From)) {
-    // Check if the variable is guaranteed a physical register.  This
-    // can happen either when the variable is pre-colored or when it is
-    // assigned infinite weight.
+    // Check if the variable is guaranteed a physical register. This can happen
+    // either when the variable is pre-colored or when it is assigned infinite
+    // weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
 template <class Machine>
 Variable *TargetX86Base<Machine>::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalizeUndef(Operand *From, int32_t RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
-    // uninitialized register; however, using an uninitialized register
-    // results in less predictable code.
+    // uninitialized register; however, using an uninitialized register results
+    // in less predictable code.
     //
-    // If in the future the implementation is changed to lower undef
-    // values to uninitialized registers, a FakeDef will be needed:
+    // If in the future the implementation is changed to lower undef values to
+    // uninitialized registers, a FakeDef will be needed:
     //     Context.insert(InstFakeDef::create(Func, Reg));
     // This is in order to ensure that the live range of Reg is not
-    // overestimated.  If the constant being lowered is a 64 bit value,
-    // then the result should be split and the lo and hi components will
-    // need to go in uninitialized registers.
+    // overestimated.  If the constant being lowered is a 64 bit value, then
+    // the result should be split and the lo and hi components will need to go
+    // in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
 
-/// For the cmp instruction, if Src1 is an immediate, or known to be a
-/// physical register, we can allow Src0 to be a memory operand.
-/// Otherwise, Src0 must be copied into a physical register.
-/// (Actually, either Src0 or Src1 can be chosen for the physical
-/// register, but unfortunately we have to commit to one or the other
-/// before register allocation.)
+/// For the cmp instruction, if Src1 is an immediate, or known to be a physical
+/// register, we can allow Src0 to be a memory operand. Otherwise, Src0 must be
+/// copied into a physical register. (Actually, either Src0 or Src1 can be
+/// chosen for the physical register, but unfortunately we have to commit to one
+/// or the other before register allocation.)
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalizeSrc0ForCmp(Operand *Src0,
                                                     Operand *Src1) {
   bool IsSrc1ImmOrReg = false;
   if (llvm::isa<Constant>(Src1)) {
     IsSrc1ImmOrReg = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src1)) {
     if (Var->hasReg())
       IsSrc1ImmOrReg = true;
   }
   return legalize(Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg);
 }
 
 template <class Machine>
 typename TargetX86Base<Machine>::Traits::X86OperandMem *
 TargetX86Base<Machine>::formMemoryOperand(Operand *Opnd, Type Ty,
                                           bool DoLegalize) {
   auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Opnd);
   // It may be the case that address mode optimization already creates an
   // Traits::X86OperandMem, so in that case it wouldn't need another level of
   // transformation.
   if (!Mem) {
     Variable *Base = llvm::dyn_cast<Variable>(Opnd);
     Constant *Offset = llvm::dyn_cast<Constant>(Opnd);
     assert(Base || Offset);
     if (Offset) {
-      // During memory operand building, we do not blind or pool
-      // the constant offset, we will work on the whole memory
-      // operand later as one entity later, this save one instruction.
-      // By turning blinding and pooling off, we guarantee
-      // legalize(Offset) will return a Constant*.
+      // During memory operand building, we do not blind or pool the constant
+      // offset, we will work on the whole memory operand later as one entity
+      // later, this save one instruction. By turning blinding and pooling off,
+      // we guarantee legalize(Offset) will return a Constant*.
       {
         BoolFlagSaver B(RandomizationPoolingPaused, true);
 
         Offset = llvm::cast<Constant>(legalize(Offset));
       }
 
       assert(llvm::isa<ConstantInteger32>(Offset) ||
              llvm::isa<ConstantRelocatable>(Offset));
     }
     Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
   }
-  // Do legalization, which contains randomization/pooling
-  // or do randomization/pooling.
+  // Do legalization, which contains randomization/pooling or do
+  // randomization/pooling.
   return llvm::cast<typename Traits::X86OperandMem>(
       DoLegalize ? legalize(Mem) : randomizeOrPoolImmediate(Mem));
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Traits::Is64Bit || Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
@@ skipping 102 matching lines @@
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
         RPI_Randomize) {
       // blind the constant
       // FROM:
       //  imm
       // TO:
       //  insert: mov imm+cookie, Reg
       //  insert: lea -cookie[Reg], Reg
       //  => Reg
       // If we have already assigned a phy register, we must come from
       // andvancedPhiLowering()=>lowerAssign(). In this case we should reuse

[Jim Stichnoth, 2015/09/16 00:01:29]

advancedPhiLowering

[ascull, 2015/09/16 18:30:09]

Done.

       // the assigned register as this assignment is that start of its use-def
-      // chain. So we add RegNum argument here.
-      // Note we use 'lea' instruction instead of 'xor' to avoid affecting
-      // the flags.
+      // chain. So we add RegNum argument here. Note we use 'lea' instruction
+      // instead of 'xor' to avoid affecting the flags.
       Variable *Reg = makeReg(IceType_i32, RegNum);
       ConstantInteger32 *Integer = llvm::cast<ConstantInteger32>(Immediate);
       uint32_t Value = Integer->getValue();
       uint32_t Cookie = Func->getConstantBlindingCookie();
       _mov(Reg, Ctx->getConstantInt(IceType_i32, Cookie + Value));
       Constant *Offset = Ctx->getConstantInt(IceType_i32, 0 - Cookie);
       _lea(Reg, Traits::X86OperandMem::create(Func, IceType_i32, Reg, Offset,
                                               nullptr, 0));
       // make sure liveness analysis won't kill this variable, otherwise a
       // liveness assertion will be triggered.
       _set_dest_nonkillable();
       if (Immediate->getType() != IceType_i32) {
         Variable *TruncReg = makeReg(Immediate->getType(), RegNum);
         _mov(TruncReg, Reg);
         return TruncReg;
       }
       return Reg;
     }
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool) {
       // pool the constant
       // FROM:
       //  imm
       // TO:
       //  insert: mov $label, Reg
       //  => Reg
       assert(Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
       Immediate->setShouldBePooled(true);
       // if we have already assigned a phy register, we must come from
       // andvancedPhiLowering()=>lowerAssign(). In this case we should reuse

[Jim Stichnoth, 2015/09/16 00:01:29]

advancedPhiLowering

[ascull, 2015/09/16 18:30:09]

Done.

       // the assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here.
       Variable *Reg = makeReg(Immediate->getType(), RegNum);
       IceString Label;
       llvm::raw_string_ostream Label_stream(Label);
       Immediate->emitPoolLabel(Label_stream);
       const RelocOffsetT Offset = 0;
       const bool SuppressMangling = true;
       Constant *Symbol =
           Ctx->getConstantSym(Offset, Label_stream.str(), SuppressMangling);
@@ skipping 13 matching lines @@
 typename TargetX86Base<Machine>::Traits::X86OperandMem *
 TargetX86Base<Machine>::randomizeOrPoolImmediate(
     typename Traits::X86OperandMem *MemOperand, int32_t RegNum) {
   assert(MemOperand);
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
-  // If this memory operand is already a randommized one, we do
-  // not randomize it again.
+  // If this memory operand is already a randommized one, we do not randomize

[Jim Stichnoth, 2015/09/16 00:01:29]

randomized

[ascull, 2015/09/16 18:30:09]

Done.

+  // it again.
   if (MemOperand->getRandomized())
     return MemOperand;
 
   if (Constant *C = llvm::dyn_cast_or_null<Constant>(MemOperand->getOffset())) {
     if (C->shouldBeRandomizedOrPooled(Ctx)) {
       // The offset of this mem operand should be blinded or pooled
       Ctx->statsUpdateRPImms();
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
           RPI_Randomize) {
         // blind the constant offset
@@ skipping 14 matching lines @@
         typename Traits::X86OperandMem *TempMemOperand =
             Traits::X86OperandMem::create(Func, MemOperand->getType(),
                                           MemOperand->getBase(), Mask1);
         // If we have already assigned a physical register, we must come from
         // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
         // the assigned register as this assignment is that start of its
         // use-def chain. So we add RegNum argument here.
         Variable *RegTemp = makeReg(MemOperand->getOffset()->getType(), RegNum);
         _lea(RegTemp, TempMemOperand);
         // As source operand doesn't use the dstreg, we don't need to add
-        // _set_dest_nonkillable().
-        // But if we use the same Dest Reg, that is, with RegNum
-        // assigned, we should add this _set_dest_nonkillable()
+        // _set_dest_nonkillable(). But if we use the same Dest Reg, that is,
+        // with RegNum assigned, we should add this _set_dest_nonkillable()
         if (RegNum != Variable::NoRegister)
           _set_dest_nonkillable();
 
         typename Traits::X86OperandMem *NewMemOperand =
             Traits::X86OperandMem::create(Func, MemOperand->getType(), RegTemp,
                                           Mask2, MemOperand->getIndex(),
                                           MemOperand->getShift(),
                                           MemOperand->getSegmentRegister());
 
         // Label this memory operand as randomized, so we won't randomize it
         // again in case we call legalize() multiple times on this memory
         // operand.
         NewMemOperand->setRandomized(true);
         return NewMemOperand;
       }
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool) {
         // pool the constant offset
         // FROM:
         //  offset[base, index, shift]
         // TO:
         //  insert: mov $label, RegTemp
         //  insert: lea [base, RegTemp], RegTemp
         //  =>[RegTemp, index, shift]
         assert(Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
                RPI_Pool);
-        // Memory operand should never exist as source operands in phi
-        // lowering assignments, so there is no need to reuse any registers
-        // here. For phi lowering, we should not ask for new physical
-        // registers in general.
-        // However, if we do meet Memory Operand during phi lowering, we
-        // should not blind or pool the immediates for now.
+        // Memory operand should never exist as source operands in phi lowering
+        // assignments, so there is no need to reuse any registers here. For
+        // phi lowering, we should not ask for new physical registers in
+        // general. However, if we do meet Memory Operand during phi lowering,
+        // we should not blind or pool the immediates for now.
         if (RegNum != Variable::NoRegister)
           return MemOperand;
         Variable *RegTemp = makeReg(IceType_i32);
         IceString Label;
         llvm::raw_string_ostream Label_stream(Label);
         MemOperand->getOffset()->emitPoolLabel(Label_stream);
         MemOperand->getOffset()->setShouldBePooled(true);
         const RelocOffsetT SymOffset = 0;
         bool SuppressMangling = true;
         Constant *Symbol = Ctx->getConstantSym(SymOffset, Label_stream.str(),
@@ skipping 25 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H