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src/IceAssemblerX86Base.h

 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 177 matching lines @@
     // Technically, Addr/GPR and Addr/Imm are also allowed, but */Addr are not.
     // In practice, we always normalize the Dest to a Register first.
     TypedEmitGPRGPR GPRGPR;
     TypedEmitGPRImm GPRImm;
   };
 
   using TypedEmitGPRGPRImm = void (AssemblerX86Base::*)(
       Type, typename Traits::GPRRegister, typename Traits::GPRRegister,
       const Immediate &);
   struct GPREmitterShiftD {
-    // Technically AddrGPR and AddrGPRImm are also allowed, but in practice
-    // we always normalize Dest to a Register first.
+    // Technically AddrGPR and AddrGPRImm are also allowed, but in practice we
+    // always normalize Dest to a Register first.
     TypedEmitGPRGPR GPRGPR;
     TypedEmitGPRGPRImm GPRGPRImm;
   };
 
   using TypedEmitAddrGPR = void (AssemblerX86Base::*)(
       Type, const typename Traits::Address &, typename Traits::GPRRegister);
   using TypedEmitAddrImm = void (AssemblerX86Base::*)(
       Type, const typename Traits::Address &, const Immediate &);
   struct GPREmitterAddrOp {
     TypedEmitAddrGPR AddrGPR;
@@ skipping 35 matching lines @@
   template <typename DReg_t, typename SReg_t> struct CastEmitterRegOp {
     using TypedEmitRegs = void (AssemblerX86Base::*)(Type, DReg_t, Type,
                                                      SReg_t);
     using TypedEmitAddr = void (AssemblerX86Base::*)(
         Type, DReg_t, Type, const typename Traits::Address &);
 
     TypedEmitRegs RegReg;
     TypedEmitAddr RegAddr;
   };
 
-  // Three operand (potentially) cross Xmm/GPR instructions.
-  // The last operand must be an immediate.
+  // Three operand (potentially) cross Xmm/GPR instructions. The last operand
+  // must be an immediate.
   template <typename DReg_t, typename SReg_t> struct ThreeOpImmEmitter {
     using TypedEmitRegRegImm = void (AssemblerX86Base::*)(Type, DReg_t, SReg_t,
                                                           const Immediate &);
     using TypedEmitRegAddrImm = void (AssemblerX86Base::*)(
         Type, DReg_t, const typename Traits::Address &, const Immediate &);
 
     TypedEmitRegRegImm RegRegImm;
     TypedEmitRegAddrImm RegAddrImm;
   };
 
@@ skipping 632 matching lines @@
                         typename Traits::GPRRegister shifter);
 
   using LabelVector = std::vector<Label *>;
   // A vector of pool-allocated x86 labels for CFG nodes.
   LabelVector CfgNodeLabels;
   // A vector of pool-allocated x86 labels for Local labels.
   LabelVector LocalLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
-  // The arith_int() methods factor out the commonality between the encodings of
-  // add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp().  The Tag
+  // The arith_int() methods factor out the commonality between the encodings
+  // of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
   // parameter is statically asserted to be less than 8.
   template <uint32_t Tag>
   void arith_int(Type Ty, typename Traits::GPRRegister reg,
                  const Immediate &imm);
 
   template <uint32_t Tag>
   void arith_int(Type Ty, typename Traits::GPRRegister reg0,
                  typename Traits::GPRRegister reg1);
 
   template <uint32_t Tag>
@@ skipping 29 matching lines @@
     static constexpr bool IsGPR =
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::ByteRegister>::value ||
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::GPRRegister>::value;
 
     return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 &&
            isByteSizedType(Ty);
   }
 
-  // assembleAndEmitRex is used for determining which (if any) rex prefix should
-  // be emitted for the current instruction. It allows different types for Reg
-  // and Rm because they could be of different types (e.g., in mov[sz]x
+  // assembleAndEmitRex is used for determining which (if any) rex prefix
+  // should be emitted for the current instruction. It allows different types
+  // for Reg and Rm because they could be of different types (e.g., in mov[sz]x
   // instrutions.) If Addr is not nullptr, then Rm is ignored, and Rex.B is

[Jim Stichnoth, 2015/09/16 00:01:29]

instructions

[ascull, 2015/09/16 18:30:09]

Done.

   // determined by Addr instead. TyRm is still used to determine Addr's size.
   template <typename RegType, typename RmType, typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type
   assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
                      const RmType Rm,
                      const typename T::Address *Addr = nullptr) {
     const uint8_t W = (TyReg == IceType_i64 || TyRm == IceType_i64)
                           ? T::Operand::RexW
                           : T::Operand::RexNone;
     const uint8_t R = (Reg & 0x08) ? T::Operand::RexR : T::Operand::RexNone;
@@ skipping 24 matching lines @@
   void emitRexRB(const Type Ty, const RegType Reg, const RmType Rm) {
     assembleAndEmitRex(Ty, Reg, Ty, Rm);
   }
 
   template <typename RegType, typename RmType>
   void emitRexRB(const Type TyReg, const RegType Reg, const Type TyRm,
                  const RmType Rm) {
     assembleAndEmitRex(TyReg, Reg, TyRm, Rm);
   }
 
-  // emitRexB is used for emitting a Rex prefix if one is needed on encoding the
-  // Reg field in an x86 instruction. It is invoked by the template when Reg is
-  // the single register operand in the instruction (e.g., push Reg.)
+  // emitRexB is used for emitting a Rex prefix if one is needed on encoding
+  // the Reg field in an x86 instruction. It is invoked by the template when
+  // Reg is the single register operand in the instruction (e.g., push Reg.)
   template <typename RmType> void emitRexB(const Type Ty, const RmType Rm) {
     emitRexRB(Ty, RexRegIrrelevant, Ty, Rm);
   }
 
   // emitRex is used for emitting a Rex prefix for an address and a GPR. The
   // address may contain zero, one, or two registers.
   template <typename RegType>
   void emitRex(const Type Ty, const typename Traits::Address &Addr,
                const RegType Reg) {
     assembleAndEmitRex(Ty, Reg, Ty, RexRegIrrelevant, &Addr);
@@ skipping 45 matching lines @@
   emitUint8(0x66);
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #include "IceAssemblerX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H