MIPS64: Fix unittests (to not use invalid load representation).

test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 470 matching lines @@
   ArchOpcode load_opcode;
   ArchOpcode store_opcode;
 };
 
 static const MemoryAccess kMemoryAccesses[] = {
     {kMachInt8, kMips64Lb, kMips64Sb},
     {kMachUint8, kMips64Lbu, kMips64Sb},
     {kMachInt16, kMips64Lh, kMips64Sh},
     {kMachUint16, kMips64Lhu, kMips64Sh},
     {kMachInt32, kMips64Lw, kMips64Sw},
-    {kRepFloat32, kMips64Lwc1, kMips64Swc1},
-    {kRepFloat64, kMips64Ldc1, kMips64Sdc1},
+    {kMachFloat32, kMips64Lwc1, kMips64Swc1},
+    {kMachFloat64, kMips64Ldc1, kMips64Sdc1},
     {kMachInt64, kMips64Ld, kMips64Sd}};
 
 
 struct MemoryAccessImm {
   MachineType type;
   ArchOpcode load_opcode;
   ArchOpcode store_opcode;
   bool (InstructionSelectorTest::Stream::*val_predicate)(
       const InstructionOperand*) const;
   const int32_t immediates[40];
@@ skipping 363 matching lines @@
   EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->InputCount());
   EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8