MIPS: Fix testcases r6_beqzc and mov.

test/cctest/test-assembler-mips.cc

Index: test/cctest/test-assembler-mips.cc
diff --git a/test/cctest/test-assembler-mips.cc b/test/cctest/test-assembler-mips.cc
index 63c9172f56688a45675bad06ff04910ddbeca928..7fd2a1d1c00deddfc0e0902e4b92fc76b239abcf 100644
--- a/test/cctest/test-assembler-mips.cc
+++ b/test/cctest/test-assembler-mips.cc
@@ -1153,17 +1153,17 @@ TEST(MIPS13) {
   MacroAssembler assm(isolate, NULL, 0);
 
   __ sw(t0, MemOperand(a0, offsetof(T, cvt_small_in)));
-  __ Cvt_d_uw(f10, t0, f22);
+  __ Cvt_d_uw(f10, t0, f16);
   __ sdc1(f10, MemOperand(a0, offsetof(T, cvt_small_out)));
 
-  __ Trunc_uw_d(f10, f10, f22);
+  __ Trunc_uw_d(f10, f10, f16);
   __ swc1(f10, MemOperand(a0, offsetof(T, trunc_small_out)));
 
   __ sw(t0, MemOperand(a0, offsetof(T, cvt_big_in)));
-  __ Cvt_d_uw(f8, t0, f22);
+  __ Cvt_d_uw(f8, t0, f16);
   __ sdc1(f8, MemOperand(a0, offsetof(T, cvt_big_out)));
 
-  __ Trunc_uw_d(f8, f8, f22);
+  __ Trunc_uw_d(f8, f8, f16);
   __ swc1(f8, MemOperand(a0, offsetof(T, trunc_big_out)));
 
   __ jr(ra);
@@ -2509,7 +2509,7 @@ TEST(sqrt_rsqrt_recip) {
     __ rsqrt_d(f14, f8);
     __ rsqrt_s(f16, f2);
     __ recip_d(f18, f8);
-    __ recip_s(f20, f2);
+    __ recip_s(f4, f2);
   }
   __ swc1(f6, MemOperand(a0, offsetof(TestFloat, resultS)) );
   __ sdc1(f12, MemOperand(a0, offsetof(TestFloat, resultD)) );
@@ -2517,7 +2517,7 @@ TEST(sqrt_rsqrt_recip) {
   if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
     __ swc1(f16, MemOperand(a0, offsetof(TestFloat, resultS1)) );
     __ sdc1(f14, MemOperand(a0, offsetof(TestFloat, resultD1)) );
-    __ swc1(f20, MemOperand(a0, offsetof(TestFloat, resultS2)) );
+    __ swc1(f4, MemOperand(a0, offsetof(TestFloat, resultS2)) );
     __ sdc1(f18, MemOperand(a0, offsetof(TestFloat, resultD2)) );
   }
   __ jr(ra);
@@ -2706,12 +2706,13 @@ TEST(mov) {
     5.3, -5.3, 5.3, -2.9
   };
 
-  __ ldc1(f2, MemOperand(a0, offsetof(TestFloat, a)) );
+  __ ldc1(f5, MemOperand(a0, offsetof(TestFloat, a)) );

[petarj, 2015/09/11 14:02:28]

Is it possible for this test to be run in fp32 mode? In case it is, you can not
use odd registers.

   __ lwc1(f6, MemOperand(a0, offsetof(TestFloat, c)) );
   __ mov_s(f18, f6);
-  __ mov_d(f20, f2);
+  __ mov_d(f17, f5);

[petarj, 2015/09/11 14:02:28]

Same here.

   __ swc1(f18, MemOperand(a0, offsetof(TestFloat, d)) );
-  __ sdc1(f20, MemOperand(a0, offsetof(TestFloat, b)) );
+  __ sdc1(f17, MemOperand(a0, offsetof(TestFloat, b)) );

[petarj, 2015/09/11 14:02:28]

Ditto.

+
   __ jr(ra);
   __ nop();
 
@@ -4678,7 +4679,6 @@ uint64_t run_beqzc(int32_t value, int32_t offset) {
   Label stop_execution;
   __ li(v0, 0);
   __ li(t1, 0x66);
-  __ push(ra);
 
   __ addiu(v0, v0, 0x1);        // <-- offset = -32
   __ addiu(v0, v0, 0x2);
@@ -4698,7 +4698,6 @@ uint64_t run_beqzc(int32_t value, int32_t offset) {
   __ nop();
 
   __ bind(&stop_execution);
-  __ pop(ra);
   __ jr(ra);
   __ nop();