Make FlushICache part of Assembler(Base) and take Isolate as parameter.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // CPU specific code for arm independent of OS goes here.
 
 #if V8_TARGET_ARCH_ARM64
 
 #include "src/arm64/utils-arm64.h"
 #include "src/assembler.h"
@@ skipping 21 matching lines @@
     // The cache type register holds the size of cache lines in words as a
     // power of two.
     return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
   }
 
   uint32_t cache_type_register_;
 };
 
 
 void CpuFeatures::FlushICache(void* address, size_t length) {
-  if (length == 0) return;
-
-  if (CpuFeatures::IsSupported(COHERENT_CACHE)) return;
-
-#ifdef USE_SIMULATOR
-  // TODO(all): consider doing some cache simulation to ensure every address
-  // run has been synced.
-  USE(address);
-  USE(length);
-#else
+#ifdef V8_HOST_ARCH_ARM64
   // The code below assumes user space cache operations are allowed. The goal
   // of this routine is to make sure the code generated is visible to the I
   // side of the CPU.
 
   uintptr_t start = reinterpret_cast<uintptr_t>(address);
   // Sizes will be used to generate a mask big enough to cover a pointer.
   CacheLineSizes sizes;
   uintptr_t dsize = sizes.dcache_line_size();
   uintptr_t isize = sizes.icache_line_size();
   // Cache line sizes are always a power of 2.
@@ skipping 46 matching lines @@
     "isb                                \n\t"
     : [dline] "+r" (dstart),
       [iline] "+r" (istart)
     : [dsize] "r"  (dsize),
       [isize] "r"  (isize),
       [end]   "r"  (end)
     // This code does not write to memory but without the dependency gcc might
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
-#endif
+#endif  // V8_HOST_ARCH_ARM64
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM64