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Side by Side Diff: src/arm/assembler-arm-inl.h

Issue 1332283002: Make FlushICache part of Assembler(Base) and take Isolate as parameter. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix arm64 PatchingAssembler that initialized its isolate with NULL :) Created 5 years, 3 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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615 615
616 616
617 void Assembler::set_target_address_at(Address pc, Address constant_pool, 617 void Assembler::set_target_address_at(Address pc, Address constant_pool,
618 Address target, 618 Address target,
619 ICacheFlushMode icache_flush_mode) { 619 ICacheFlushMode icache_flush_mode) {
620 if (is_constant_pool_load(pc)) { 620 if (is_constant_pool_load(pc)) {
621 // This is a constant pool lookup. Update the entry in the constant pool. 621 // This is a constant pool lookup. Update the entry in the constant pool.
622 Memory::Address_at(constant_pool_entry_address(pc, constant_pool)) = target; 622 Memory::Address_at(constant_pool_entry_address(pc, constant_pool)) = target;
623 // Intuitively, we would think it is necessary to always flush the 623 // Intuitively, we would think it is necessary to always flush the
624 // instruction cache after patching a target address in the code as follows: 624 // instruction cache after patching a target address in the code as follows:
625 // CpuFeatures::FlushICache(pc, sizeof(target)); 625 // Assembler::FlushICacheWithoutIsolate(pc, sizeof(target));
626 // However, on ARM, no instruction is actually patched in the case 626 // However, on ARM, no instruction is actually patched in the case
627 // of embedded constants of the form: 627 // of embedded constants of the form:
628 // ldr ip, [pp, #...] 628 // ldr ip, [pp, #...]
629 // since the instruction accessing this address in the constant pool remains 629 // since the instruction accessing this address in the constant pool remains
630 // unchanged. 630 // unchanged.
631 } else if (CpuFeatures::IsSupported(ARMv7)) { 631 } else if (CpuFeatures::IsSupported(ARMv7)) {
632 // This is an movw / movt immediate load. Patch the immediate embedded in 632 // This is an movw / movt immediate load. Patch the immediate embedded in
633 // the instructions. 633 // the instructions.
634 DCHECK(IsMovW(Memory::int32_at(pc))); 634 DCHECK(IsMovW(Memory::int32_at(pc)));
635 DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize))); 635 DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
636 uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc); 636 uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
637 uint32_t immediate = reinterpret_cast<uint32_t>(target); 637 uint32_t immediate = reinterpret_cast<uint32_t>(target);
638 instr_ptr[0] = PatchMovwImmediate(instr_ptr[0], immediate & 0xFFFF); 638 instr_ptr[0] = PatchMovwImmediate(instr_ptr[0], immediate & 0xFFFF);
639 instr_ptr[1] = PatchMovwImmediate(instr_ptr[1], immediate >> 16); 639 instr_ptr[1] = PatchMovwImmediate(instr_ptr[1], immediate >> 16);
640 DCHECK(IsMovW(Memory::int32_at(pc))); 640 DCHECK(IsMovW(Memory::int32_at(pc)));
641 DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize))); 641 DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
642 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 642 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
643 CpuFeatures::FlushICache(pc, 2 * kInstrSize); 643 Assembler::FlushICacheWithoutIsolate(pc, 2 * kInstrSize);
644 } 644 }
645 } else { 645 } else {
646 // This is an mov / orr immediate load. Patch the immediate embedded in 646 // This is an mov / orr immediate load. Patch the immediate embedded in
647 // the instructions. 647 // the instructions.
648 DCHECK(IsMovImmed(Memory::int32_at(pc)) && 648 DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
649 IsOrrImmed(Memory::int32_at(pc + kInstrSize)) && 649 IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
650 IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) && 650 IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
651 IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize))); 651 IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
652 uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc); 652 uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
653 uint32_t immediate = reinterpret_cast<uint32_t>(target); 653 uint32_t immediate = reinterpret_cast<uint32_t>(target);
654 instr_ptr[0] = PatchShiftImm(instr_ptr[0], immediate & kImm8Mask); 654 instr_ptr[0] = PatchShiftImm(instr_ptr[0], immediate & kImm8Mask);
655 instr_ptr[1] = PatchShiftImm(instr_ptr[1], immediate & (kImm8Mask << 8)); 655 instr_ptr[1] = PatchShiftImm(instr_ptr[1], immediate & (kImm8Mask << 8));
656 instr_ptr[2] = PatchShiftImm(instr_ptr[2], immediate & (kImm8Mask << 16)); 656 instr_ptr[2] = PatchShiftImm(instr_ptr[2], immediate & (kImm8Mask << 16));
657 instr_ptr[3] = PatchShiftImm(instr_ptr[3], immediate & (kImm8Mask << 24)); 657 instr_ptr[3] = PatchShiftImm(instr_ptr[3], immediate & (kImm8Mask << 24));
658 DCHECK(IsMovImmed(Memory::int32_at(pc)) && 658 DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
659 IsOrrImmed(Memory::int32_at(pc + kInstrSize)) && 659 IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
660 IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) && 660 IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
661 IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize))); 661 IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
662 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 662 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
663 CpuFeatures::FlushICache(pc, 4 * kInstrSize); 663 Assembler::FlushICacheWithoutIsolate(pc, 4 * kInstrSize);
664 } 664 }
665 } 665 }
666 } 666 }
667 667
668 668
669 } } // namespace v8::internal 669 } } // namespace v8::internal
670 670
671 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ 671 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_
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