Implements int2fp, fp2int, and fp2fp conversions for ARM32.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 359 matching lines @@
 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
                                Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Umull, 2, DestLo, Predicate),
       // DestHi is expected to have a FakeDef inserted by the lowering code.
       DestHi(DestHi) {
   addSource(Src0);
   addSource(Src1);
 }
 
+InstARM32Vcvt::InstARM32Vcvt(Cfg *Func, Variable *Dest, Variable *Src,
+                             VcvtVariant Variant, CondARM32::Cond Predicate)
+    : InstARM32Pred(Func, InstARM32::Vcvt, 1, Dest, Predicate),
+      Variant(Variant) {
+  addSource(Src);
+}
+
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Clz::Opcode = "clz";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 template <> const char *InstARM32Rbit::Opcode = "rbit";
 template <> const char *InstARM32Rev::Opcode = "rev";
@@ skipping 512 matching lines @@
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = ";
   dumpOpcodePred(Str, "umull", getDest()->getType());
   Str << " ";
   dumpSources(Func);
 }
 
+namespace {
+const char *vcvtVariantSuffix(const InstARM32Vcvt::VcvtVariant Variant) {
+  switch (Variant) {
+  case InstARM32Vcvt::S2si:
+    return ".s32.f32";
+  case InstARM32Vcvt::S2ui:
+    return ".u32.f32";
+  case InstARM32Vcvt::Si2s:
+    return ".f32.s32";
+  case InstARM32Vcvt::Ui2s:
+    return ".f32.u32";
+  case InstARM32Vcvt::D2si:
+    return ".s32.f64";
+  case InstARM32Vcvt::D2ui:
+    return ".u32.f64";
+  case InstARM32Vcvt::Si2d:
+    return ".f64.s32";
+  case InstARM32Vcvt::Ui2d:
+    return ".f64.u32";
+  case InstARM32Vcvt::S2d:
+    return ".f64.f32";
+  case InstARM32Vcvt::D2s:
+    return ".f32.f64";
+  }
+  llvm::report_fatal_error("Invalid VcvtVariant enum.");
+}
+} // end of anonymous namespace
+
+void InstARM32Vcvt::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 1);
+  assert(getDest()->hasReg());
+  Str << "\t"
+      << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+}
+
+void InstARM32Vcvt::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Vcvt::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  dumpDest(Func);
+  Str << " = "
+      << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << " ";
+  dumpSources(Func);
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
     Str << "], ";
@@ skipping 96 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice