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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #if V8_TARGET_ARCH_PPC | 5 #if V8_TARGET_ARCH_PPC |
6 | 6 |
7 #include "src/codegen.h" | 7 #include "src/codegen.h" |
8 #include "src/ic/ic.h" | 8 #include "src/ic/ic.h" |
9 #include "src/ic/ic-compiler.h" | 9 #include "src/ic/ic-compiler.h" |
10 #include "src/ic/stub-cache.h" | 10 #include "src/ic/stub-cache.h" |
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704 __ bind(&maybe_name_key); | 704 __ bind(&maybe_name_key); |
705 __ LoadP(r7, FieldMemOperand(key, HeapObject::kMapOffset)); | 705 __ LoadP(r7, FieldMemOperand(key, HeapObject::kMapOffset)); |
706 __ lbz(r7, FieldMemOperand(r7, Map::kInstanceTypeOffset)); | 706 __ lbz(r7, FieldMemOperand(r7, Map::kInstanceTypeOffset)); |
707 __ JumpIfNotUniqueNameInstanceType(r7, &slow); | 707 __ JumpIfNotUniqueNameInstanceType(r7, &slow); |
708 | 708 |
709 if (FLAG_vector_stores) { | 709 if (FLAG_vector_stores) { |
710 // The handlers in the stub cache expect a vector and slot. Since we won't | 710 // The handlers in the stub cache expect a vector and slot. Since we won't |
711 // change the IC from any downstream misses, a dummy vector can be used. | 711 // change the IC from any downstream misses, a dummy vector can be used. |
712 Register vector = VectorStoreICDescriptor::VectorRegister(); | 712 Register vector = VectorStoreICDescriptor::VectorRegister(); |
713 Register slot = VectorStoreICDescriptor::SlotRegister(); | 713 Register slot = VectorStoreICDescriptor::SlotRegister(); |
714 DCHECK(!AreAliased(vector, slot, r6, r7, r8, r9)); | 714 DCHECK(!AreAliased(vector, slot, r8, r9, r10, r11)); |
715 Handle<TypeFeedbackVector> dummy_vector = | 715 Handle<TypeFeedbackVector> dummy_vector = |
716 TypeFeedbackVector::DummyVector(masm->isolate()); | 716 TypeFeedbackVector::DummyVector(masm->isolate()); |
717 int slot_index = dummy_vector->GetIndex( | 717 int slot_index = dummy_vector->GetIndex( |
718 FeedbackVectorICSlot(TypeFeedbackVector::kDummyKeyedStoreICSlot)); | 718 FeedbackVectorICSlot(TypeFeedbackVector::kDummyKeyedStoreICSlot)); |
719 __ LoadRoot(vector, Heap::kDummyVectorRootIndex); | 719 __ LoadRoot(vector, Heap::kDummyVectorRootIndex); |
720 __ LoadSmiLiteral(slot, Smi::FromInt(slot_index)); | 720 __ LoadSmiLiteral(slot, Smi::FromInt(slot_index)); |
721 } | 721 } |
722 | 722 |
723 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags( | 723 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags( |
724 Code::ComputeHandlerFlags(Code::STORE_IC)); | 724 Code::ComputeHandlerFlags(Code::STORE_IC)); |
725 masm->isolate()->stub_cache()->GenerateProbe(masm, Code::STORE_IC, flags, | 725 masm->isolate()->stub_cache()->GenerateProbe(masm, Code::STORE_IC, flags, |
726 receiver, key, r6, r7, r8, r9); | 726 receiver, key, r8, r9, r10, r11); |
727 // Cache miss. | 727 // Cache miss. |
728 __ b(&miss); | 728 __ b(&miss); |
729 | 729 |
730 // Extra capacity case: Check if there is extra capacity to | 730 // Extra capacity case: Check if there is extra capacity to |
731 // perform the store and update the length. Used for adding one | 731 // perform the store and update the length. Used for adding one |
732 // element to the array by writing to array[array.length]. | 732 // element to the array by writing to array[array.length]. |
733 __ bind(&extra); | 733 __ bind(&extra); |
734 // Condition code from comparing key and array length is still available. | 734 // Condition code from comparing key and array length is still available. |
735 __ bne(&slow); // Only support writing to writing to array[array.length]. | 735 __ bne(&slow); // Only support writing to writing to array[array.length]. |
736 // Check for room in the elements backing store. | 736 // Check for room in the elements backing store. |
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799 int args = FLAG_vector_stores ? 5 : 3; | 799 int args = FLAG_vector_stores ? 5 : 3; |
800 __ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1); | 800 __ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1); |
801 } | 801 } |
802 | 802 |
803 | 803 |
804 void StoreIC::GenerateNormal(MacroAssembler* masm) { | 804 void StoreIC::GenerateNormal(MacroAssembler* masm) { |
805 Label miss; | 805 Label miss; |
806 Register receiver = StoreDescriptor::ReceiverRegister(); | 806 Register receiver = StoreDescriptor::ReceiverRegister(); |
807 Register name = StoreDescriptor::NameRegister(); | 807 Register name = StoreDescriptor::NameRegister(); |
808 Register value = StoreDescriptor::ValueRegister(); | 808 Register value = StoreDescriptor::ValueRegister(); |
809 Register dictionary = r6; | 809 Register dictionary = r8; |
810 DCHECK(receiver.is(r4)); | 810 DCHECK(receiver.is(r4)); |
811 DCHECK(name.is(r5)); | 811 DCHECK(name.is(r5)); |
812 DCHECK(value.is(r3)); | 812 DCHECK(value.is(r3)); |
| 813 DCHECK(VectorStoreICDescriptor::VectorRegister().is(r6)); |
| 814 DCHECK(VectorStoreICDescriptor::SlotRegister().is(r7)); |
813 | 815 |
814 __ LoadP(dictionary, FieldMemOperand(receiver, JSObject::kPropertiesOffset)); | 816 __ LoadP(dictionary, FieldMemOperand(receiver, JSObject::kPropertiesOffset)); |
815 | 817 |
816 GenerateDictionaryStore(masm, &miss, dictionary, name, value, r7, r8); | 818 GenerateDictionaryStore(masm, &miss, dictionary, name, value, r9, r10); |
817 Counters* counters = masm->isolate()->counters(); | 819 Counters* counters = masm->isolate()->counters(); |
818 __ IncrementCounter(counters->store_normal_hit(), 1, r7, r8); | 820 __ IncrementCounter(counters->store_normal_hit(), 1, r9, r10); |
819 __ Ret(); | 821 __ Ret(); |
820 | 822 |
821 __ bind(&miss); | 823 __ bind(&miss); |
822 __ IncrementCounter(counters->store_normal_miss(), 1, r7, r8); | 824 __ IncrementCounter(counters->store_normal_miss(), 1, r9, r10); |
823 GenerateMiss(masm); | 825 GenerateMiss(masm); |
824 } | 826 } |
825 | 827 |
826 | 828 |
827 #undef __ | 829 #undef __ |
828 | 830 |
829 | 831 |
830 Condition CompareIC::ComputeCondition(Token::Value op) { | 832 Condition CompareIC::ComputeCondition(Token::Value op) { |
831 switch (op) { | 833 switch (op) { |
832 case Token::EQ_STRICT: | 834 case Token::EQ_STRICT: |
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919 patcher.EmitCondition(ne); | 921 patcher.EmitCondition(ne); |
920 } else { | 922 } else { |
921 DCHECK(Assembler::GetCondition(branch_instr) == ne); | 923 DCHECK(Assembler::GetCondition(branch_instr) == ne); |
922 patcher.EmitCondition(eq); | 924 patcher.EmitCondition(eq); |
923 } | 925 } |
924 } | 926 } |
925 } // namespace internal | 927 } // namespace internal |
926 } // namespace v8 | 928 } // namespace v8 |
927 | 929 |
928 #endif // V8_TARGET_ARCH_PPC | 930 #endif // V8_TARGET_ARCH_PPC |
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