MIPS: Fixing illegal use of at register

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index 783d311b8b720f0eec2c520b3017faee46d17746..ce6f278540fd30f2095130a3555b16b7c6248680 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -2026,6 +2026,8 @@ void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
 void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // load to two 32-bit loads.
+  DCHECK(!src.rm().is(at));
+  DCHECK(!src.rm().is(t8));

[paul.l..., 2015/09/08 15:48:41]

Why check for t8 here? You do not use it in this function.

This then requires the change to macro-asm LeaveExitFrame which is not really
needed.

[Djordje.Pesic, 2015/09/09 06:41:54]

DCHECK(!src.rm().is(t8)) removed. Macro-asm LeeaveExitFrame also changed to old
version with t8.

   if (IsFp64Mode()) {
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(LWC1, src.rm(), fd,
@@ -2071,6 +2073,8 @@ void Assembler::swc1(FPURegister fd, const MemOperand& src) {
 void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // store to two 32-bit stores.
+  DCHECK(!src.rm().is(at));
+  DCHECK(!src.rm().is(t8));
   if (IsFp64Mode()) {
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(SWC1, src.rm(), fd,