MIPS: Fixing illegal use of at register

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2006 matching lines @@
   } else {  // Offset > 16 bits, use multiple instructions to load.
     LoadRegPlusOffsetToAt(src);
     GenInstrImmediate(LWC1, at, fd, 0);
   }
 }
 
 
 void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // load to two 32-bit loads.
+  CHECK(!src.rm().is(at));

[paul.l..., 2015/08/31 22:56:34]

I think these should be DCHECK (here and below).

[Djordje.Pesic, 2015/09/07 11:34:17]

Done.

   if (IsFp64Mode()) {
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(LWC1, src.rm(), fd,
                         src.offset_ + Register::kMantissaOffset);
       GenInstrImmediate(LW, src.rm(), at,
                         src.offset_ + Register::kExponentOffset);
       mthc1(at, fd);
     } else {  // Offset > 16 bits, use multiple instructions to load.
       LoadRegPlusOffsetToAt(src);
       GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
@@ skipping 25 matching lines @@
   } else {  // Offset > 16 bits, use multiple instructions to load.
     LoadRegPlusOffsetToAt(src);
     GenInstrImmediate(SWC1, at, fd, 0);
   }
 }
 
 
 void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // store to two 32-bit stores.
+  CHECK(!src.rm().is(at));
   if (IsFp64Mode()) {
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(SWC1, src.rm(), fd,
                         src.offset_ + Register::kMantissaOffset);
       mfhc1(at, fd);
       GenInstrImmediate(SW, src.rm(), at,
                         src.offset_ + Register::kExponentOffset);
     } else {  // Offset > 16 bits, use multiple instructions to load.
       LoadRegPlusOffsetToAt(src);
       GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
       mfhc1(t8, fd);

[paul.l..., 2015/08/31 22:56:34]

Note the use of t8 here. (t8 is reserved for macro-assembler use, but this is
probably ok, as ldc1 and sdc1 _should_ be moved to macro-assembler anyway (as
Ldc1() and Sdc1(), I will create an issue for that.)

It might make sense to add another DCHECK within this block:
DCHECK(!src.rm().is(t8));

[Djordje.Pesic, 2015/09/07 11:34:17]

Done.

       GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
     }
   } else {  // fp32 mode.
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(SWC1, src.rm(), fd,
                         src.offset_ + Register::kMantissaOffset);
       FPURegister nextfpreg;
       nextfpreg.setcode(fd.code() + 1);
       GenInstrImmediate(SWC1, src.rm(), nextfpreg,
                         src.offset_ + Register::kExponentOffset);
@@ skipping 998 matching lines @@
   if (patched) {
     CpuFeatures::FlushICache(pc + 2, sizeof(Address));
   }
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS