A64: Synchronize with r17635.

src/a64/assembler-a64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 221 matching lines @@
   return sregisters[code];
 }
 
 
 inline const FPRegister& FPRegister::DRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfFPRegisters);
   return dregisters[code];
 }
 
 
-inline const Register& CPURegister::W() {
+inline const Register& CPURegister::W() const {
   ASSERT(IsValidRegister());
   return Register::WRegFromCode(code_);
 }
 
 
-inline const Register& CPURegister::X() {
+inline const Register& CPURegister::X() const {
   ASSERT(IsValidRegister());
   return Register::XRegFromCode(code_);
 }
 
 
-inline const FPRegister& CPURegister::S() {
+inline const FPRegister& CPURegister::S() const {
   ASSERT(IsValidFPRegister());
   return FPRegister::SRegFromCode(code_);
 }
 
 
-inline const FPRegister& CPURegister::D() {
+inline const FPRegister& CPURegister::D() const {
   ASSERT(IsValidFPRegister());
   return FPRegister::DRegFromCode(code_);
 }
 
 
 // Operand.
 #define DECLARE_INT_OPERAND_CONSTRUCTOR(type)                                  \
 Operand::Operand(type immediate, RelocInfo::Mode rmode)                        \
     : immediate_(immediate),                                                   \
       reg_(NoReg),                                                             \
@@ skipping 223 matching lines @@
 
 
 Address Assembler::target_pointer_address_at(Address pc) {
   Instruction* instr = reinterpret_cast<Instruction*>(pc);
   ASSERT(instr->IsLdrLiteralX());
   return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
 }
 
 
 // Read/Modify the code target address in the branch/call instruction at pc.
-Address Assembler::target_pointer_at(Address pc) {
+Address Assembler::target_address_at(Address pc) {
   return Memory::Address_at(target_pointer_address_at(pc));
 }
 
 
 Address Assembler::target_address_from_return_address(Address pc) {
   // Returns the address of the call target from the return address that will
   // be returned to after a call.
   // Call sequence on A64 is:
   //  ldr ip0, #... @ load from literal pool
   //  blr ip0
@@ skipping 36 matching lines @@
     return pc + Assembler::kCallSizeWithoutRelocation;
   } else {
     // Verify the instruction sequence.
     ASSERT(instr->IsLdrLiteralX());
     ASSERT(instr->following(1)->IsBranchAndLinkToRegister());
     return pc + Assembler::kCallSizeWithRelocation;
   }
 }
 
 
-Address Assembler::target_address_at(Address pc) {
-  return target_pointer_at(pc);
-}
-
-
-void Assembler::set_target_address_at(Address pc, Address target) {
-  set_target_pointer_at(pc, target);
-}
-
-
 void Assembler::deserialization_set_special_target_at(
     Address constant_pool_entry, Address target) {
   Memory::Address_at(constant_pool_entry) = target;
 }
 
 
 void Assembler::set_external_target_at(Address constant_pool_entry,
                                        Address target) {
   Memory::Address_at(constant_pool_entry) = target;
 }
 
 
-void Assembler::set_target_pointer_at(Address pc, Address target) {
+void Assembler::set_target_address_at(Address pc, Address target) {
   Memory::Address_at(target_pointer_address_at(pc)) = target;
   // Intuitively, we would think it is necessary to always flush the
   // instruction cache after patching a target address in the code as follows:
   //   CPU::FlushICache(pc, sizeof(target));
   // However, on ARM, an instruction is actually patched in the case of
   // embedded constants of the form:
   // ldr   ip, [pc, #...]
   // since the instruction accessing this address in the constant pool remains
   // unchanged, a flush is not required.
 }
@@ skipping 13 matching lines @@
 Address RelocInfo::target_address_address() {
   ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
                               || rmode_ == EMBEDDED_OBJECT
                               || rmode_ == EXTERNAL_REFERENCE);
   return Assembler::target_pointer_address_at(pc_);
 }
 
 
 Object* RelocInfo::target_object() {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
-  return reinterpret_cast<Object*>(Assembler::target_pointer_at(pc_));
+  return reinterpret_cast<Object*>(Assembler::target_address_at(pc_));
 }
 
 
 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
   return Handle<Object>(reinterpret_cast<Object**>(
-      Assembler::target_pointer_at(pc_)));
+      Assembler::target_address_at(pc_)));
 }
 
 
 void RelocInfo::set_target_object(Object* target, WriteBarrierMode mode) {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
   ASSERT(!target->IsConsString());
-  Assembler::set_target_pointer_at(pc_, reinterpret_cast<Address>(target));
+  Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target));
   if (mode == UPDATE_WRITE_BARRIER &&
       host() != NULL &&
       target->IsHeapObject()) {
     host()->GetHeap()->incremental_marking()->RecordWrite(
         host(), &Memory::Object_at(pc_), HeapObject::cast(target));
   }
 }
 
 
 Address RelocInfo::target_reference() {
@@ skipping 81 matching lines @@
         host(), this, HeapObject::cast(target_code));
   }
 }
 
 
 void RelocInfo::WipeOut() {
   ASSERT(IsEmbeddedObject(rmode_) ||
          IsCodeTarget(rmode_) ||
          IsRuntimeEntry(rmode_) ||
          IsExternalReference(rmode_));
-  Assembler::set_target_pointer_at(pc_, NULL);
+  Assembler::set_target_address_at(pc_, NULL);
 }
 
 
 bool RelocInfo::IsPatchedReturnSequence() {
   // The sequence must be:
   //   ldr ip0, [pc, #offset]
   //   blr ip0
   // See a64/debug-a64.cc BreakLocationIterator::SetDebugBreakAtReturn().
   Instruction* i1 = reinterpret_cast<Instruction*>(pc_);
   Instruction* i2 = i1->following();
@@ skipping 410 matching lines @@
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_ASSEMBLER_A64_INL_H_