MIPS:[turbofan] Improve boolean materialization compares.

src/compiler/mips64/code-generator-mips64.cc

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index bcfa56ae306a19c0bdff67ff51807be6c8296563..c897f1caeb59b4817e1eeebfcf3e24a819313967 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -201,32 +201,45 @@ class OutOfLineCeil final : public OutOfLineRound {
 };
 
 
-Condition FlagsConditionToConditionCmp(FlagsCondition condition) {
+Condition FlagsConditionToConditionCmp(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kEqual:
+      predicate = true;
       return eq;
     case kNotEqual:
+      predicate = false;
       return ne;
     case kSignedLessThan:
+      predicate = true;
       return lt;
     case kSignedGreaterThanOrEqual:
+      predicate = false;
       return ge;
     case kSignedLessThanOrEqual:
+      predicate = false;
       return le;
     case kSignedGreaterThan:
+      predicate = true;
       return gt;
     case kUnsignedLessThan:
+      predicate = true;
       return lo;
     case kUnsignedGreaterThanOrEqual:
+      predicate = false;
       return hs;
     case kUnsignedLessThanOrEqual:
+      predicate = false;
       return ls;
     case kUnsignedGreaterThan:
+      predicate = true;
       return hi;
     case kUnorderedEqual:
     case kUnorderedNotEqual:
+      predicate = true;
       break;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
@@ -234,13 +247,17 @@ Condition FlagsConditionToConditionCmp(FlagsCondition condition) {
 }
 
 
-Condition FlagsConditionToConditionTst(FlagsCondition condition) {
+Condition FlagsConditionToConditionTst(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kNotEqual:
+      predicate = false;
       return ne;
     case kEqual:
+      predicate = true;
       return eq;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
@@ -248,13 +265,17 @@ Condition FlagsConditionToConditionTst(FlagsCondition condition) {
 }
 
 
-Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
+Condition FlagsConditionToConditionOvf(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kOverflow:
+      predicate = true;
       return ne;
     case kNotOverflow:
+      predicate = false;
       return eq;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
@@ -975,7 +996,7 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   Label* tlabel = branch->true_label;
   Label* flabel = branch->false_label;
   Condition cc = kNoCondition;
-
+  bool predicate;
   // MIPS does not have condition code flags, so compare and branch are
   // implemented differently than on the other arch's. The compare operations
   // emit mips psuedo-instructions, which are handled here by branch
@@ -984,17 +1005,17 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   // they are tested here.
 
   if (instr->arch_opcode() == kMips64Tst) {
-    cc = FlagsConditionToConditionTst(branch->condition);
+    cc = FlagsConditionToConditionTst(predicate, branch->condition);
     __ And(at, i.InputRegister(0), i.InputOperand(1));
     __ Branch(tlabel, cc, at, Operand(zero_reg));
   } else if (instr->arch_opcode() == kMips64Dadd ||
              instr->arch_opcode() == kMips64Dsub) {
-    cc = FlagsConditionToConditionOvf(branch->condition);
+    cc = FlagsConditionToConditionOvf(predicate, branch->condition);
     __ dsra32(kScratchReg, i.OutputRegister(), 0);
     __ sra(at, i.OutputRegister(), 31);
     __ Branch(tlabel, cc, at, Operand(kScratchReg));
   } else if (instr->arch_opcode() == kMips64Cmp) {
-    cc = FlagsConditionToConditionCmp(branch->condition);
+    cc = FlagsConditionToConditionCmp(predicate, branch->condition);
     __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));
   } else if (instr->arch_opcode() == kMips64CmpS) {
     if (!convertCondition(branch->condition, cc)) {
@@ -1034,39 +1055,111 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
   DCHECK_NE(0u, instr->OutputCount());
   Register result = i.OutputRegister(instr->OutputCount() - 1);
   Condition cc = kNoCondition;
-
+  bool predicate;
   // MIPS does not have condition code flags, so compare and branch are
   // implemented differently than on the other arch's. The compare operations
   // emit mips pseudo-instructions, which are checked and handled here.
 
-  // For materializations, we use delay slot to set the result true, and
-  // in the false case, where we fall through the branch, we reset the result
-  // false.
-
   if (instr->arch_opcode() == kMips64Tst) {
-    cc = FlagsConditionToConditionTst(condition);
-    __ And(at, i.InputRegister(0), i.InputOperand(1));
-    __ Branch(USE_DELAY_SLOT, &done, cc, at, Operand(zero_reg));
-    __ li(result, Operand(1));  // In delay slot.
+    cc = FlagsConditionToConditionTst(predicate, condition);
+    __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));
+    __ xori(kScratchReg2, zero_reg, 1);  // Create 1 for true.
+    if (kArchVariant != kMips64r6) {
+      if (predicate) {
+        __ Movn(result, zero_reg, kScratchReg);
+        __ Movz(result, kScratchReg2, kScratchReg);
+      } else {
+        __ Movz(result, zero_reg, kScratchReg);
+        __ Movn(result, kScratchReg2, kScratchReg);
+      }
+    } else {
+      if (predicate) {
+        __ seleqz(result, kScratchReg2, kScratchReg);
+      } else {
+        __ selnez(result, kScratchReg2, kScratchReg);
+      }
+    }
+    return;
   } else if (instr->arch_opcode() == kMips64Dadd ||
              instr->arch_opcode() == kMips64Dsub) {
-    cc = FlagsConditionToConditionOvf(condition);
-    __ dsra32(kScratchReg, i.OutputRegister(), 0);
-    __ sra(at, i.OutputRegister(), 31);
-    __ Branch(USE_DELAY_SLOT, &done, cc, at, Operand(kScratchReg));
-    __ li(result, Operand(1));  // In delay slot.
+    FlagsConditionToConditionOvf(predicate, condition);
+    // Check for overflow creates 1 or 0 for result.
+    __ dsrl32(kScratchReg, i.OutputRegister(), 31);
+    __ srl(at, i.OutputRegister(), 31);
+    __ xor_(result, kScratchReg, at);
+    if (!predicate)  // Toggle result for not overflow.
+      __ xori(result, result, 1);
+    return;
   } else if (instr->arch_opcode() == kMips64Cmp) {
-    Register left = i.InputRegister(0);
-    Operand right = i.InputOperand(1);
-    cc = FlagsConditionToConditionCmp(condition);
-    __ Branch(USE_DELAY_SLOT, &done, cc, left, right);
-    __ li(result, Operand(1));  // In delay slot.
+    cc = FlagsConditionToConditionCmp(predicate, condition);
+    switch (cc) {
+      case eq:
+      case ne: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Dsubu(kScratchReg, left, right);
+        __ xori(kScratchReg2, zero_reg, 1);
+        if (kArchVariant != kMips64r6) {
+          if (predicate) {
+            __ Movn(result, zero_reg, kScratchReg);
+            __ Movz(result, kScratchReg2, kScratchReg);
+          } else {
+            __ Movz(result, zero_reg, kScratchReg);
+            __ Movn(result, kScratchReg2, kScratchReg);
+          }
+        } else {
+          if (predicate) {
+            __ seleqz(result, kScratchReg2, kScratchReg);
+          } else {
+            __ selnez(result, kScratchReg2, kScratchReg);
+          }
+        }
+      } break;
+      case lt:
+      case ge: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Slt(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case gt:
+      case le: {
+        Register left = i.InputRegister(1);
+        Operand right = i.InputOperand(0);
+        __ Slt(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case lo:
+      case hs: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Sltu(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case hi:
+      case ls: {
+        Register left = i.InputRegister(1);
+        Operand right = i.InputOperand(0);
+        __ Sltu(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      default:
+        UNREACHABLE();
+    }
+    return;
   } else if (instr->arch_opcode() == kMips64CmpD ||
              instr->arch_opcode() == kMips64CmpS) {
     FPURegister left = i.InputDoubleRegister(0);
     FPURegister right = i.InputDoubleRegister(1);
 
-    bool predicate;
     FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate, condition);
     if (kArchVariant != kMips64r6) {
       __ li(result, Operand(1));
@@ -1100,10 +1193,6 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
     TRACE_UNIMPL();
     UNIMPLEMENTED();
   }
-  // Fallthru case is the false materialization.
-  __ bind(&false_value);
-  __ li(result, Operand(static_cast<int64_t>(0)));
-  __ bind(&done);
 }