Updates and fixes for MIPS support.

src/mips/constants-mips.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 172 matching lines @@
     default:
       return false;
   };
 }
 
 
 bool Instruction::IsLinkingInstruction() {
   int op = OpcodeFieldRaw();
   switch (op) {
     case JAL:
-    case BGEZAL:
-    case BLTZAL:
-      return true;
+    case REGIMM:
+      switch (RtFieldRaw()) {
+        case BGEZAL:
+        case BLTZAL:
+          return true;
+      default:
+        return false;
+      };
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JALR:
           return true;
         default:
           return false;
       };
     default:
       return false;
   };
@@ skipping 48 matching lines @@
         case XOR:
         case NOR:
         case SLT:
         case SLTU:
         case TGE:
         case TGEU:
         case TLT:
         case TLTU:
         case TEQ:
         case TNE:
+        case MOVZ:
+        case MOVN:
           return kRegisterType;
         default:
           UNREACHABLE();
       };
       break;
     case SPECIAL2:
       switch (FunctionFieldRaw()) {
         case MUL:
+        case CLZ:
+          return kRegisterType;
+        default:
+          UNREACHABLE();
+      };
+      break;
+    case SPECIAL3:
+      switch (FunctionFieldRaw()) {
+        case INS:
+        case EXT:
           return kRegisterType;
         default:
           UNREACHABLE();
       };
       break;
     case COP1:    // Coprocessor instructions
-      switch (FunctionFieldRaw()) {
+      switch (RsFieldRawNoAssert()) {
         case BC1:   // branch on coprocessor condition
           return kImmediateType;
         default:
           return kRegisterType;
       };
       break;
     // 16 bits Immediate type instructions. eg: addi dest, src, imm16
     case REGIMM:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
     case ADDI:
     case ADDIU:
     case SLTI:
     case SLTIU:
     case ANDI:
     case ORI:
     case XORI:
     case LUI:
     case BEQL:
     case BNEL:
     case BLEZL:
     case BGTZL:
     case LB:
+    case LH:
     case LW:
     case LBU:
+    case LHU:
     case SB:
+    case SH:
     case SW:
     case LWC1:
     case LDC1:
     case SWC1:
     case SDC1:
       return kImmediateType;
     // 26 bits immediate type instructions. eg: j imm26
     case J:
     case JAL:
       return kJumpType;
     default:
       UNREACHABLE();
   };
   return kUnsupported;
 }
 
+
+// -----------------------------------------------------------------------------
+// MIPS Assembly utils.
+
+int32_t ISA_utils_instr_at(int32_t* pc) { return *pc; }
+int32_t* ISA_utils_target_address_at(int32_t* pc) {
+  int32_t instr1 = ISA_utils_instr_at(pc);
+  int32_t instr2 = ISA_utils_instr_at(pc + 1);
+  // Check we have 2 instructions generated by li.
+  if (((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) ||
+     ((instr1 == nopInstr) && ((instr2 & kOpcodeMask) == ADDI ||
+                               (instr2 & kOpcodeMask) == ORI ||
+                               (instr2 & kOpcodeMask) == LUI))) {
+    // Interpret these 2 instructions.
+    if (instr1 == nopInstr) {
+      if ((instr2 & kOpcodeMask) == ADDI) {
+        return reinterpret_cast<int32_t*>(((instr2 & kImm16Mask) << 16) >> 16);
+      } else if ((instr2 & kOpcodeMask) == ORI) {
+        return reinterpret_cast<int32_t*>(instr2 & kImm16Mask);
+      } else if ((instr2 & kOpcodeMask) == LUI) {
+        return reinterpret_cast<int32_t*>((instr2 & kImm16Mask) << 16);
+      }
+    } else if ((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) {
+      // 32 bits value.
+      return reinterpret_cast<int32_t*>(
+          (instr1 & kImm16Mask) << 16 | (instr2 & kImm16Mask));
+    }
+
+    // We should never get here.
+    UNREACHABLE();
+    return reinterpret_cast<int32_t*>(0x0);
+
+  } else {
+    return reinterpret_cast<int32_t*>(*pc);
+  }
+}
+
+
 } }   // namespace assembler::mips