Subzero. Changes the Register Allocator so that it is aware of register

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file declares the TargetLoweringX86 template class, which
 /// implements the TargetLowering base interface for the x86
 /// architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 
 #include "IceDefs.h"
 #include "IceInst.h"
 #include "IceSwitchLowering.h"
 #include "IceTargetLowering.h"
 #include "IceUtils.h"
 
+#include <array>
 #include <type_traits>
 #include <utility>
 
 namespace Ice {
 namespace X86Internal {
 
 template <class MachineTraits> class BoolFolding;
 
 template <class Machine> struct MachineTraits {};
 
@@ skipping 32 matching lines @@
   SizeT getNumRegisters() const override {
     return Traits::RegisterSet::Reg_NUM;
   }
   Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
   IceString getRegName(SizeT RegNum, Type Ty) const override;
   llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                       RegSetMask Exclude) const override;
   const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
     return TypeToRegisterSet[Ty];
   }
+
+  const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
+    assert(Reg < Traits::RegisterSet::Reg_NUM);
+    return RegisterAliases[Reg];
+  }
+
   bool hasFramePointer() const override { return IsEbpBasedFrame; }
   SizeT getFrameOrStackReg() const override {
     return IsEbpBasedFrame ? Traits::RegisterSet::Reg_ebp
                            : Traits::RegisterSet::Reg_esp;
   }
   size_t typeWidthInBytesOnStack(Type Ty) const override {
     // Round up to the next multiple of WordType bytes.
     const uint32_t WordSizeInBytes = typeWidthInBytes(Traits::WordType);
     return Utils::applyAlignment(typeWidthInBytes(Ty), WordSizeInBytes);
   }
@@ skipping 585 matching lines @@
   };
 
   bool optimizeScalarMul(Variable *Dest, Operand *Src0, int32_t Src1);
   void findRMW();
 
   typename Traits::InstructionSet InstructionSet =
       Traits::InstructionSet::Begin;
   bool IsEbpBasedFrame = false;
   bool NeedsStackAlignment = false;
   size_t SpillAreaSizeBytes = 0;
-  llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
+  std::array<llvm::SmallBitVector, IceType_NUM> TypeToRegisterSet;
+  std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
+      RegisterAliases;
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
-  VarList PhysicalRegisters[IceType_NUM];
+  std::array<VarList, IceType_NUM> PhysicalRegisters;
 
   /// Randomize a given immediate operand
   Operand *randomizeOrPoolImmediate(Constant *Immediate,
                                     int32_t RegNum = Variable::NoRegister);
   typename Traits::X86OperandMem *
   randomizeOrPoolImmediate(typename Traits::X86OperandMem *MemOperand,
                            int32_t RegNum = Variable::NoRegister);
   bool RandomizationPoolingPaused = false;
 
 private:
@@ skipping 20 matching lines @@
   }
 
   BoolFolding FoldingInfo;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H