Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(660)

Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1319203005: Subzero. Changes the Register Allocator so that it is aware of register (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 5 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/IceTargetLoweringARM32.h ('k') | src/IceTargetLoweringMIPS32.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 169 matching lines...) Expand 10 before | Expand all | Expand 10 after
180 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM); 180 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
181 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM); 181 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
182 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); 182 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
183 ScratchRegs.resize(RegARM32::Reg_NUM); 183 ScratchRegs.resize(RegARM32::Reg_NUM);
184 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 184 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
185 isFP32, isFP64, isVec128) \ 185 isFP32, isFP64, isVec128) \
186 IntegerRegisters[RegARM32::val] = isInt; \ 186 IntegerRegisters[RegARM32::val] = isInt; \
187 Float32Registers[RegARM32::val] = isFP32; \ 187 Float32Registers[RegARM32::val] = isFP32; \
188 Float64Registers[RegARM32::val] = isFP64; \ 188 Float64Registers[RegARM32::val] = isFP64; \
189 VectorRegisters[RegARM32::val] = isVec128; \ 189 VectorRegisters[RegARM32::val] = isVec128; \
190 RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM); \
191 RegisterAliases[RegARM32::val].set(RegARM32::val); \
190 ScratchRegs[RegARM32::val] = scratch; 192 ScratchRegs[RegARM32::val] = scratch;
191 REGARM32_TABLE; 193 REGARM32_TABLE;
192 #undef X 194 #undef X
193 TypeToRegisterSet[IceType_void] = InvalidRegisters; 195 TypeToRegisterSet[IceType_void] = InvalidRegisters;
194 TypeToRegisterSet[IceType_i1] = IntegerRegisters; 196 TypeToRegisterSet[IceType_i1] = IntegerRegisters;
195 TypeToRegisterSet[IceType_i8] = IntegerRegisters; 197 TypeToRegisterSet[IceType_i8] = IntegerRegisters;
196 TypeToRegisterSet[IceType_i16] = IntegerRegisters; 198 TypeToRegisterSet[IceType_i16] = IntegerRegisters;
197 TypeToRegisterSet[IceType_i32] = IntegerRegisters; 199 TypeToRegisterSet[IceType_i32] = IntegerRegisters;
198 TypeToRegisterSet[IceType_i64] = IntegerRegisters; 200 TypeToRegisterSet[IceType_i64] = IntegerRegisters;
199 TypeToRegisterSet[IceType_f32] = Float32Registers; 201 TypeToRegisterSet[IceType_f32] = Float32Registers;
(...skipping 2839 matching lines...) Expand 10 before | Expand all | Expand 10 after
3039 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; 3041 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n";
3040 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { 3042 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
3041 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; 3043 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n";
3042 } 3044 }
3043 // Technically R9 is used for TLS with Sandboxing, and we reserve it. 3045 // Technically R9 is used for TLS with Sandboxing, and we reserve it.
3044 // However, for compatibility with current NaCl LLVM, don't claim that. 3046 // However, for compatibility with current NaCl LLVM, don't claim that.
3045 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 3047 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
3046 } 3048 }
3047 3049
3048 } // end of namespace Ice 3050 } // end of namespace Ice
OLDNEW
« no previous file with comments | « src/IceTargetLoweringARM32.h ('k') | src/IceTargetLoweringMIPS32.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698