Subzero. Changes the Register Allocator so that it is aware of register

src/IceRegAlloc.h

 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 78 matching lines @@
   void handleNoFreeRegisters(IterationState &Iter);
   void assignFinalRegisters(const llvm::SmallBitVector &RegMaskFull,
                             const llvm::SmallBitVector &PreDefinedRegisters,
                             bool Randomized);
   /// @}
 
   void dumpLiveRangeTrace(const char *Label, const Variable *Item);
 
   Cfg *const Func;
   GlobalContext *const Ctx;
+  TargetLowering *const Target;
 
   OrderedRanges Unhandled;
   /// UnhandledPrecolored is a subset of Unhandled, specially collected for
   /// faster processing.
   OrderedRanges UnhandledPrecolored;
   UnorderedRanges Active, Inactive, Handled;
   std::vector<InstNumberT> Kills;
   RegAllocKind Kind = RAK_Unknown;
   /// RegUses[I] is the number of live ranges (variables) that register I is
   /// currently assigned to. It can be greater than 1 as a result of
   /// AllowOverlap inference.
   llvm::SmallVector<int32_t, REGS_SIZE> RegUses;
+  // TODO(jpp): for some architectures a SmallBitVector might not be big enough.
+  // Evaluate what the performance impact on tose architectures is.

[Jim Stichnoth, 2015/09/04 18:19:24]

those

[John, 2015/09/04 18:23:21]

Done.

+  llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases;
   bool FindPreference = false;
   bool FindOverlap = false;
 
   const bool Verbose;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGALLOC_H