Compute the loop nest depth of each CfgNode and weight Variables by it.

src/IceTargetLoweringX86BaseImpl.h

Index: src/IceTargetLoweringX86BaseImpl.h
diff --git a/src/IceTargetLoweringX86BaseImpl.h b/src/IceTargetLoweringX86BaseImpl.h
index afbbaf3c4cf15e16e68184838043034bd8a17c0c..f70a936c65e5e87ec61280759ceb7c6169307dd9 100644
--- a/src/IceTargetLoweringX86BaseImpl.h
+++ b/src/IceTargetLoweringX86BaseImpl.h
@@ -327,6 +327,13 @@ template <class Machine> void TargetX86Base<Machine>::translateO2() {
     Func->dump("After Phi lowering");
   }
 
+  // Run this early so it can be used to focus optimizations on potentially hot
+  // code.

[jvoung (off chromium), 2015/09/01 18:56:18]

Some new nodes are created later, but I suppose those don't require the loop
analysis information.

+  // TODO: currently only used for regalloc not expensive high level

[Jim Stichnoth, 2015/09/01 22:17:38]

TODO(ascull,stichnot)

[ascull, 2015/09/03 19:52:38]

Done.

+  // optimizations which could be focused on potentially hot code.
+  Func->computeLoopNestDepth();
+  Func->dump("After loop nest depth analysis");
+
   // Address mode optimization.
   Func->getVMetadata()->init(VMK_SingleDefs);
   Func->doAddressOpt();
@@ -367,8 +374,9 @@ template <class Machine> void TargetX86Base<Machine>::translateO2() {
     return;
   Func->dump("After x86 codegen");
 
-  // Register allocation.  This requires instruction renumbering and full
-  // liveness analysis.
+  // Register allocation. This requires instruction renumbering and full
+  // liveness analysis. Loops must be identified before livness to variable use

[jvoung (off chromium), 2015/09/01 18:56:18]

"livness"

something sounds odd about "Loops must be identified before liveness to variable
use weights are correct"

[Jim Stichnoth, 2015/09/01 22:17:38]

I think you mean "so variable use"?

[ascull, 2015/09/03 19:52:38]

Done.

+  // weights are correct.
   Func->renumberInstructions();
   if (Func->hasError())
     return;