MIPS: Refine '[es6] Introduce a dedicated JSIteratorResult type.'

MIPS: Refine '[es6] Introduce a dedicated JSIteratorResult type.'

Port 72bc4b5c8a5c4279bcb8b340edbc8aa1c46d75a1

Original commit message:
Use a single JSIteratorResult type for all implementation provided
iterator results (i.e. the String, Array and collection iterators,
and also for generators).  This removes one source of unnecessary
polymorphism in for-of loops.  It is accomplished by a new intrinsic
%_CreateIterResultObject() that should be used to create iterator
result objects from JavaScript builtins (there's a matching factory
method for C++ code).

Also restructure the %StringIteratorPrototype%.next() and
%ArrayIteratorPrototype%.next() functions to be a bit more friendly
to optimizing compilers.

BUG=

Committed: https://crrev.com/29a2e8f861bdb1be40704205027becac1c4e72e5
Cr-Commit-Position: refs/heads/master@{#30572}

[balazs.kilvady, 2015-09-03 15:49:16]

balazs.kilvady@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, bmeurer@chromium.org, danno@chromium.org,
paul.lind@imgtec.com

[paul.l..., 2015-09-03 16:41:42]

LGTM.

FYI, for Benedikt and v8 team, LoadRoot() is preferred over li() where possible,
since it is one instruction vs two.

MIPS64 ABI (n64) has 8 argument registers rather than the 4 on MIPS32 ABI, and
the "conventional names" for registers 4 thru 15 were therefore changed from
[a0-a3][t0-t7] to [a0-a7][t0-t3]. So the "next available register" after 'a3'
changes between MIPS32 and MIPS64.

[balazs.kilvady, 2015-09-03 16:59:58]

The CQ bit was checked by balazs.kilvady@imgtec.com

[commit-bot: I haz the power, 2015-09-03 17:00:11]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1315903005/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1315903005/1

[Benedikt Meurer, 2015-09-03 17:39:40]

> FYI, for Benedikt and v8 team, LoadRoot() is preferred over li() where
possible,
> since it is one instruction vs two.
> 
> MIPS64 ABI (n64) has 8 argument registers rather than the 4 on MIPS32 ABI, and
> the "conventional names" for registers 4 thru 15 were therefore changed from
> [a0-a3][t0-t7] to [a0-a7][t0-t3]. So the "next available register" after 'a3'
> changes between MIPS32 and MIPS64.

Thanks for the hints, Paul.

[commit-bot: I haz the power, 2015-09-03 17:51:21]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2015-09-03 17:51:41]

Patchset 1 (id:??) landed as
https://crrev.com/29a2e8f861bdb1be40704205027becac1c4e72e5
Cr-Commit-Position: refs/heads/master@{#30572}